STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 5

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ
9.7
9.8
9.9
9.10
9.11
9.12
9.13
Serial controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI slave mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Inter-integrated circuit (I2C) interface registers . . . . . . . . . . . . . . . . . . . . 98
Universal asynchronous receiver / transmitter (UART) registers . . . . . . 100
DMA channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.6.3
9.6.4
9.6.5
Direct memory access (DMA) channels . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.8.1
9.8.2
9.8.3
9.8.4
SPI master mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.11.1
9.11.2
9.11.3
9.12.1
9.12.2
9.12.3
9.12.4
9.13.1
9.13.2
9.13.3
9.13.4
9.13.5
9.13.6
9.13.7
9.13.8
9.13.9
9.13.10 Receive DMA end address register A (SCx_RXENDA) . . . . . . . . . . . . 108
RTS/CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Serial mode register (SCx_MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Serial controller interrupt flag register (INT_SCxFLAG) . . . . . . . . . . . . 93
Serial controller interrupt configuration register (INT_SCxCFG) . . . . . . 94
Serial controller interrupt mode register (SCx_INTMODE) . . . . . . . . . . 95
Serial data register (SCx_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SPI configuration register (SCx_SPICFG) . . . . . . . . . . . . . . . . . . . . . . . 96
SPI status register (SCx_SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Serial clock linear prescaler register (SCx_RATELIN) . . . . . . . . . . . . . . 97
Serial clock exponential prescaler register (SCx_RATEEXP) . . . . . . . . 98
I2C status register (SCx_TWISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
I2C control 1 register (SCx_TWICTRL1) . . . . . . . . . . . . . . . . . . . . . . . . 99
I2C control 2 register (SCx_TWICTRL2) . . . . . . . . . . . . . . . . . . . . . . . . 99
UART status register (SC1_UARTSTAT) . . . . . . . . . . . . . . . . . . . . . . . 100
UART configuration register (SC1_UARTCFG) . . . . . . . . . . . . . . . . . . 101
UART baud rate period register (SC1_UARTPER) . . . . . . . . . . . . . . . 102
UART baud rate fractional period register (SC1_UARTFRAC) . . . . . . 102
Serial DMA control register (SCx_DMACTRL) . . . . . . . . . . . . . . . . . . 103
Serial DMA status register (SCx_DMASTAT) . . . . . . . . . . . . . . . . . . . 104
Transmit DMA begin address register A (SCx_TXBEGA) . . . . . . . . . . 105
Transmit DMA begin address register B (SCx_TXBEGB) . . . . . . . . . . 105
Transmit DMA end address register A (SCx_TXENDA) . . . . . . . . . . . 106
Transmit DMA end address register B (SCx_TXENDB) . . . . . . . . . . . 106
Transmit DMA count register (SCx_TXCNT) . . . . . . . . . . . . . . . . . . . . 106
Receive DMA begin address register A (SCx_RXBEGA) . . . . . . . . . . 107
Receive DMA begin address register B (SCx_RXBEGB) . . . . . . . . . . 107
Doc ID 16252 Rev 9
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