Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 85

• Manufacturer Part Number: Z84C0010PEG
• Description: IC 10MHZ Z80 CMOS CPU 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C0010PEG

• Processor Type: Z80
• Features: Enhanced Z80 Microprocessor/CPU
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 100°C
• Rohs Compliant: Yes
• Processor Series: Z84C0xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 10MHz
• Frequency Typ: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3898; Z84C0010PEG

UM008005-0205
Three types of register indirect jumps are also included. These
instructions are implemented by loading the register pair HL or one of the
index registers 1X or IY directly into the PC. This feature allows for
program jumps to be a function of previous calculations.
A call is a special form of a jump where the address of the byte following
the call instruction is pushed onto the stack before the jump is made. A
return instruction is the reverse of a call because the data on the top of the
stack is popped directly into the PC to form a jump address. The call and
return instructions allow for simple subroutine and interrupt handling.
Two special return instruction are included in the Z80 family of
components. The return from interrupt instruction (
from nonmaskable interrupt (
unconditional return identical to the Op Code
(
peripheral chips recognize the execution of this instruction for proper
control of nested priority interrupt handling. This instruction, coupled
with the Z80 peripheral devices implementation, simplifies the normal
return from nested interrupt. Without this feature, the following software
sequence is necessary to inform the interrupting device that the interrupt
routine is completed:
This seven byte sequence can be replaced with the one byte
and the two byte
interrupt service time often must be minimized.
Table 15. Bit Manipulation Group
Disable Interrupt
LD A, n
OUT n, A
Enable Interrupt
Return
RETI
Bit
) can be used at the end of an interrupt routine and all Z80
Register Addressing
A
8
Prevent interrupt before routine is exited.
Notify peripheral that service
routine is complete.
RETI
C
instruction in the Z80. This is important because
D
RETN
E
) are treated in the CPU as an
H
Z80 CPU Instruction Description
L
C9H
. The difference is that
RETI
Reg. Indir.
(HL)
User’s Manual
) and the return
EI
Indexed
(IX+d)
DD
Z80 CPU
instruction
(IY+d)
FD
65