Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 37

IC 10MHZ Z80 CMOS CPU 40-DIP

Z84C0010PEG

Manufacturer Part Number
Z84C0010PEG
Description
IC 10MHZ Z80 CMOS CPU 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheets

Specifications of Z84C0010PEG

Processor Type
Z80
Features
Enhanced Z80 Microprocessor/CPU
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Operating Temperature Max
100°C
Rohs Compliant
Yes
Processor Series
Z84C0xx
Core
Z80
Data Bus Width
8 bit
Program Memory Size
64 KB
Maximum Clock Frequency
10 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
10MHz
Frequency Typ
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3898
Z84C0010PEG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z84C0010PEG
Manufacturer:
Zilog
Quantity:
110
Part Number:
Z84C0010PEG
Manufacturer:
Zilog
Quantity:
203
Part Number:
Z84C0010PEG
Manufacturer:
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UM008005-0205
Non-Maskable Interrupt Response
A
D
15
7
MREQ
IORQ
WAIT
— A
— D
CLK
RD
INT
M1
Figure 9.
Figure 10 illustrates the request/acknowledge cycle for the non-maskable
interrupt. This signal is sampled at the same time as the interrupt line, but
this line takes priority over the normal interrupt and it can not be disabled
under software control. Its usual function is to provide immediate response
to important signals such as an impending power failure. The CPU response
to a non-maskable interrupt is similar to a normal memory read operation.
The only difference is that the content of the data bus is ignored while the
processor automatically stores the PC in the external stack and jumps to
location
begin at this location if this interrupt is used.
0
0
Last M Cycle of Instruction
0066H
Interrupt Request/Acknowledge Cycle
Last T State
. The service routine for the non-maskable interrupt must
T
1
T
PC
2
M1
T
W*
User’s Manual
T
W*
Z80 CPU
In
Overview
Refresh
T
3
17

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