Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 40

• Manufacturer Part Number: Z84C0010PEG
• Description: IC 10MHZ Z80 CMOS CPU 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C0010PEG

• Processor Type: Z80
• Features: Enhanced Z80 Microprocessor/CPU
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 100°C
• Rohs Compliant: Yes
• Processor Series: Z84C0xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 10MHz
• Frequency Typ: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3898; Z84C0010PEG

20
UM008005-0205
Z80 CPU
User’s Manual
Power-Down Release Cycle
RESET
HALT
HALT
CLK
NMI
M1
CLK
The system clock must be supplied to the CMOS Z80 CPU to release the
power-down state. When the system clock is supplied to the CLK input, the
CMOS Z80 CPU restarts operations from the point at which the power-
down state was implemented. The timing diagrams for the release from
power-down mode are featured in Figure 13 , 14 and 15.
When the HALT instruction is executed to enter the power-down state, the
CMOS Z80 CPU also enters the HALT state. An interrupt signal (either
NMI or ANT) or a RESET signal must be applied to the CPU after the
system clock is supplied in order to release the power-down state.
Figure 13. Power-Down Release Cycle No. 1
Figure 14. Power-Down Release Cycle No. 2
M1
T
1
T
2
T
3
T
4
T
1
T
1
T
2
T
3
Overview
T
4