Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 285
Z84C0010PEG
Manufacturer Part Number
Z84C0010PEG
Description
IC 10MHZ Z80 CMOS CPU 40-DIP
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C0010PEG
Processor Type
Z80
Features
Enhanced Z80 Microprocessor/CPU
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Operating Temperature Max
100°C
Rohs Compliant
Yes
Processor Series
Z84C0xx
Core
Z80
Data Bus Width
8 bit
Program Memory Size
64 KB
Maximum Clock Frequency
10 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
10MHz
Frequency Typ
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3898
Z84C0010PEG
Z84C0010PEG
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Quantity
Price
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Operation:
Op Code:
Description: This instruction is used at the end of a non-maskable interrupts service
Condition Bits Affected: None
Example:
UM008005-0205
Return from non maskable interrupt
RETN
routine to restore the contents of the Program Counter (PC) (analogous to
the RET instruction). The state of IFF2 is copied back to IFF1 so that
maskable interrupts are enabled immediately following the RETN if they
were enabled before the nonmaskable interrupt.
If the contents of the Stack Pointer are
Program Counter are
is received, the CPU ignores the next instruction and instead restarts to
memory address
is pushed onto the external stack address of
byte first, and
begins an interrupt service routine that ends with a
Upon the execution of
popped off the external memory stack, low order first, resulting in a Stack
Pointer contents again of
left off with an Op Code fetch to address
0066H is loaded onto the Program Counter. That address begins an
interrupt service routine that ends with a
RETN
memory stack, low order first, resulting in a Stack Pointer contents again of
1
0
the former Program Counter contents are popped off the external
1
1
M Cycles
1
0
4
0066H
0
0
0066H
1A45H
1
0
is loaded onto the Program Counter. That address
. The current Program Counter contents of
RETN
RETN
1000H
14 (4, 4, 3, 3)
1
1
T States
, when a non maskable interrupt (NMI) signal
the former Program Counter contents are
0
0
. The program flow continues where it
1
1
1000H
RETN
ED
45
1A45H
0FFFH
, and the contents of the
4 MHz E.T.
instruction. At execution of
, order-byte first, and
3.50
and
RETN
0FFEH
Z80 Instruction Set
User’s Manual
instruction.
, high order-
Z80 CPU
1A45H
265
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