Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 283

IC 10MHZ Z80 CMOS CPU 40-DIP

Z84C0010PEG

Manufacturer Part Number
Z84C0010PEG
Description
IC 10MHZ Z80 CMOS CPU 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheets

Specifications of Z84C0010PEG

Processor Type
Z80
Features
Enhanced Z80 Microprocessor/CPU
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Operating Temperature Max
100°C
Rohs Compliant
Yes
Processor Series
Z84C0xx
Core
Z80
Data Bus Width
8 bit
Program Memory Size
64 KB
Maximum Clock Frequency
10 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
10MHz
Frequency Typ
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3898
Z84C0010PEG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z84C0010PEG
Manufacturer:
Zilog
Quantity:
110
Part Number:
Z84C0010PEG
Manufacturer:
Zilog
Quantity:
203
Part Number:
Z84C0010PEG
Manufacturer:
ZILOG
Quantity:
20 000
Operation:
Op Code:
Description: This instruction is used at the end of a maskable interrupt service routine to:
Condition Bits Affected: None
Example:
UM008005-0205
Return from Interrupt
RETI
Given: Two interrupting devices, with A and B connected in a daisy-chain
configuration and A having a higher priority than B.
+
1
INT
0
Restore the contents of the Program Counter (PC) (analogous to the
RET instruction)
Signal an I/O device that the interrupt routine is completed. The
instruction also facilitates the nesting of interrupts, allowing higher
priority devices to temporarily suspend service of lower priority
service routines. However, this instruction does not enable interrupts
that were disabled when the interrupt routine was entered. Before
doing the
should be executed to allow recognition of interrupts after completion
of the current service routine.
IEI
1
1
M Cycles
A
1
0
4
RETI
IEO
0
0
instruction, the enable interrupt instruction (
1
1
RETI
14 (4, 4, 3, 3)
1
1
T States
IEI
0
0
B
1
1
IEO
ED
4D
4 MHz E.T.
3.50
Z80 Instruction Set
User’s Manual
Z80 CPU
EI
)
RETI
263

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