Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 306

• Manufacturer Part Number: Z84C0010PEG
• Description: IC 10MHZ Z80 CMOS CPU 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C0010PEG

• Processor Type: Z80
• Features: Enhanced Z80 Microprocessor/CPU
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 100°C
• Rohs Compliant: Yes
• Processor Series: Z84C0xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 10MHz
• Frequency Typ: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3898; Z84C0010PEG

286
Operation:
Op Code:
Description: The contents of the HL register pair are placed on the address bus to select a
UM008005-0205
Z80 CPU
User’s Manual
(C) ← (HL), B ← B - 1, HL ← HL - 1
OTDR
location in memory. The byte contained in this memory location is tempo-
rarily stored in the CPU. Then, after the byte counter (B) is decremented,
the contents of register C are placed on the bottom half (A0 through A7) of
the address bus to select the I/O device at one of 256 possible ports. Regis-
ter B may be used as a byte counter, and its decremented value is placed on
the top half (A8 through A15) of the address bus at this time. Next, the byte
to be output is placed on the data bus and written to the selected peripheral
device. Then, register pair HL is decremented and if the decremented B
register is not zero, the Program Counter (PC) is decremented by two and
the instruction is repeated. If B has gone to zero, the instruction is termi-
nated. Interrupts are recognized and two refresh cycles are executed after
each data transfer.
If B ≠ 0:
If B = 0:
1
1
1
0
Note: When B is set to zero prior to instruction execution, the instruc-
tion outputs 256 bytes of data.
M Cycles
M Cycles
1
1
5
4
0
1
1
1
21 (4, 5, 3, 4, 5)
OTDR
16 (4, 5, 3, 4)
1
0
T States
T States
0
1
1
1
ED
BB
4 MHz E.T.
4 MHz E.T.
5.25
4.00
Z80 Instruction Set