Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 76

• Manufacturer Part Number: Z84C0010PEG
• Description: IC 10MHZ Z80 CMOS CPU 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C0010PEG

• Processor Type: Z80
• Features: Enhanced Z80 Microprocessor/CPU
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 100°C
• Rohs Compliant: Yes
• Processor Series: Z84C0xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 10MHz
• Frequency Typ: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3898; Z84C0010PEG

56
UM008005-0205
Z80 CPU
User’s Manual
Table 8. Exchanges EX and EXX
Block Transfer and Search
Table 9 lists the extremely powerful block transfer instructions. These
instructions operate with three registers.
•
•
•
After the programmer initializes these three registers, any of these four
instructions can be used. The
moves one byte from the location pointed to by HL to the location pointed
to by DE. Register pairs HL and DE are then automatically incremented
and are ready to point to the following locations. The byte counter
(register pair BC) is also decremented at this time. This instruction is
valuable when blocks of data must be moved but other types of
processing are required between each move. The
and Repeat) instruction is an extension of the
load and increment operation is repeated until the byte counter reaches the
count of zero. Thus, this single instruction can move any block of data
from one location to any other.
IMPLIED
REG.
IND.
HL
DE
BC
points to the source location
points to the destination location
is a byte counter
AF
BC
DE
HL
DE
(SP)
AF'
08
BC', DE', and HL' HL
D9
LDI
Implied Addressing
(Load and Increment) instruction
Z80 CPU Instruction Description
LDI
EB
E3
LDIR
instruction. The same
IX
DD
E3
(Load, Increment
IY
FD
E3