Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 51

IC 10MHZ Z80 CMOS CPU 40-DIP

Z84C0010PEG

Manufacturer Part Number
Z84C0010PEG
Description
IC 10MHZ Z80 CMOS CPU 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheets

Specifications of Z84C0010PEG

Processor Type
Z80
Features
Enhanced Z80 Microprocessor/CPU
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Operating Temperature Max
100°C
Rohs Compliant
Yes
Processor Series
Z84C0xx
Core
Z80
Data Bus Width
8 bit
Program Memory Size
64 KB
Maximum Clock Frequency
10 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
10MHz
Frequency Typ
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3898
Z84C0010PEG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z84C0010PEG
Manufacturer:
Zilog
Quantity:
110
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Z84C0010PEG
Manufacturer:
Zilog
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203
Part Number:
Z84C0010PEG
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UM008005-0205
Interfacing Dynamic Memories
CLK
MREQ
Figure 20. Adding One Wait State to Any Memory Cycle
Each individual dynamic RAM has it’s own specifications that require
minor modifications to the examples given here. ZiLOG Application Notes
are available describing how the Z80 CPU is interfaced with most popular
dynamic RAM.
Figure 21 illustrates the logic necessary to interface 8 Kbytes of dynamic
RAM using 18-pin 4K dynamic memories. This logic assumes that the
RAMs are the only memory in the system so that A12 is used to select
between the two pages of memory. During refresh time, all memories in the
system must be read. The CPU provides the correct refresh address on lines
A0 through A6. When adding more memory to the system, it is necessary
to replace only the two gates that operate on A12 with a decoder that oper-
ates on all required address bits. Address buffers and data bus buffers are
generally required for larger systems.
D
C
7474
+5V
S
R
+5V
Q
Q
D
C
7474
+5V
S
R
+5V
Q
Q
Hardware and Software Implementation Examples
7400
WAIT
MREQ
CLK
WAIT
User’s Manual
T
1
Z80 CPU
T
2
T
W
31

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