Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 53

• Manufacturer Part Number: Z84C0010PEG
• Description: IC 10MHZ Z80 CMOS CPU 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C0010PEG

• Processor Type: Z80
• Features: Enhanced Z80 Microprocessor/CPU
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 100°C
• Rohs Compliant: Yes
• Processor Series: Z84C0xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 10MHz
• Frequency Typ: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3898; Z84C0010PEG

SOFTWARE IMPLEMENTATION EXAMPLES
UM008005-0205
Overview of Software Features
The Z80 instruction set provides the user with a large number of operations
to control the Z80 CPU. The main alternate and index registers can hold
arithmetic and logical operations, form memory addresses, or act as fast-
access storage for frequently used data.
Information can be moved directly from register to register, from memory
to memory, from memory to registers, or from registers to memory. In addi-
tion, register contents and register/memory contents can be exchanged
without using temporary storage. In particular, the contents of main and
alternate registers can be completely exchanged by executing only two
instructions,
separate the set of working registers from different logical procedures or to
expand the set of available registers in a single procedure.
Storage and retrieval of data between pairs of registers and memory can be
controlled on a last-in first-out basis through
that utilize a special
available both to manipulate data and to automatically store and retrieve
addresses for subroutine linkage. When a subroutine is called, for example,
the address following the
down stack pointed to by
routine, the address on the top of the stack is used to set the program
counter for the address of the next instruction. The stack pointer is adjusted
automatically to reflect the current top stack position during
CALL
stacks and subroutine calls to be nested to any practical depth because the
stack area can potentially be as large as memory space.
The sequence of instruction execution can be controlled by six different
flags (carry, zero, sign, parity/overflow, add/subtract, half-carry), which
reflect the results of arithmetic, logical, shift, and compare instructions.
, and
RET
EX
instructions. This stack mechanism allows pushdown data
and
STACK POINTER
EXX
Hardware and Software Implementation Examples
. This register exchange procedure can be used to
SP
CALL
. When a subroutine returns to the calling
instruction is placed on the top of the push-
register (SP). This stack register is
PUSH
and
POP
User’s Manual
instructions
PUSH
Z80 CPU
,
POP
,
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