Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 33

• Manufacturer Part Number: Z84C0010PEG
• Description: IC 10MHZ Z80 CMOS CPU 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C0010PEG

• Processor Type: Z80
• Features: Enhanced Z80 Microprocessor/CPU
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 100°C
• Rohs Compliant: Yes
• Processor Series: Z84C0xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 10MHz
• Frequency Typ: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3898; Z84C0010PEG

UM008005-0205
A
D
15
7
MREQ
RFSH
WAIT
— D
— A
CLK
RD
M1
Memory Read Or Write
0
0
segments from being gated onto the data bus. The MREQ signal during
refresh time should be used to perform a refresh read of all memory
elements. The refresh signal can not be used by itself because the refresh
address is only guaranteed to be stable during MREQ time.
Figure 5.
Figure 6 illustrates the timing of memory read or write cycles other than an
Op Code fetch cycle. These cycles are generally three clock periods long
unless wait states are requested by the memory through the WAIT signal.
The MREQ signal and the RD signal are used the same as in the fetch cycle.
In a memory write cycle, the MREQ also becomes active when the address
bus is stable so that it can be used directly as a chip enable for dynamic
memories. The WR line is active when data on the data bus is stable so that
T
PC
1
Instruction Op Code Fetch
T
2
M1 Cycle
IN
T
3
Refresh Address
T
4
T
User’s Manual
1
Z80 CPU
Overview
13