Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 242

IC 10MHZ Z80 CMOS CPU 40-DIP

Z84C0010PEG

Manufacturer Part Number
Z84C0010PEG
Description
IC 10MHZ Z80 CMOS CPU 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheets

Specifications of Z84C0010PEG

Processor Type
Z80
Features
Enhanced Z80 Microprocessor/CPU
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Operating Temperature Max
100°C
Rohs Compliant
Yes
Processor Series
Z84C0xx
Core
Z80
Data Bus Width
8 bit
Program Memory Size
64 KB
Maximum Clock Frequency
10 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
10MHz
Frequency Typ
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3898
Z84C0010PEG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z84C0010PEG
Manufacturer:
Zilog
Quantity:
110
Part Number:
Z84C0010PEG
Manufacturer:
Zilog
Quantity:
203
Part Number:
Z84C0010PEG
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Quantity:
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222
Operation:
Op Code:
Operands:
Description: The contents of the low order four bits (bits 3, 2, 1, and 0) of memory
Condition Bits Affected:
UM008005-0205
Z80 CPU
User’s Manual
A
RRD
location (HL) are copied to the low order four bits of the Accumulator
(register A). The previous contents of the low order four bits of the
Accumulator are copied to the high order four bits (7, 6, 5, and 4) of
location (HL); and the previous contents of the high order four bits of (HL)
are copied to the low order four bits of (HL). The contents of the high order
bits of the Accumulator are unaffected.
(HL) means the memory location specified by the contents of the HL
register pair.
S is set if Accumulator is negative after operation; reset otherwise
Z is set if Accumulator is zero after operation; reset otherwise
H is reset
P/V is set if parity of Accumulator is even after operation; reset otherwise
N is reset
C is not affected
1
0
7
4
1
1
M Cycles
3
1
1
0
5
7
0
0
4
1
0
3
18 (4, 4, 3, 4, 3)
0
RRD
1
1
T States
(HL)
0
1
1
1
ED
67
4 MHz E.T.
4.50
Z80 Instruction Set

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