Z84C0010PEG Zilog, Z84C0010PEG Datasheet - Page 31

• Manufacturer Part Number: Z84C0010PEG
• Description: IC 10MHZ Z80 CMOS CPU 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C0010PEG

• Processor Type: Z80
• Features: Enhanced Z80 Microprocessor/CPU
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 100°C
• Rohs Compliant: Yes
• Processor Series: Z84C0xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 10MHz
• Frequency Typ: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3898; Z84C0010PEG

TIMING
UM008005-0205
Overview
The Z80 CPU executes instructions by stepping through a precise set of
basic operations. These include:
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•
•
All instructions are series of basic operations. Each of these operations can
take from three to six clock periods to complete or they can be lengthened to
synchronize the CPU to the speed of external devices. The clock periods are
referred to as T (time) cycles and the operations are referred to as M
(machine) cycles. Figure 4 illustrates how a typical instruction is series of
specific M and T cycles. Notice that this instruction consists of three
machine cycles (M1, M2, and M3). The first machine cycle of any
instruction is a fetch cycle which is four, five, or six T cycles long (unless
lengthened by the WAIT signal, which is described in the next section). The
fetch cycle (M1) is used to fetch the opcode of the next instruction to be
executed. Subsequent machine cycles move data between the CPU and
memory or I/O devices, and they may have anywhere from three to five T
cycles (again, they may be lengthened by wait states to synchronize the
external devices to the CPU). The following paragraphs describe the timing
which occurs within any of the basic machine cycles.
During T2 and every subsequent Tw, the CPU samples the WAIT line with
the falling edge of Clock. If the WAIT line is active at this time, another
WAIT state is entered during the following cycle. Using this technique, the
read can be lengthened to match the access time of any type of memory
device.
Memory Read or Write
I/O Device Read or Write
Interrupt Acknowledge
User’s Manual
Z80 CPU
Overview
11