EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 82

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

4–2
Table 4–1. Summary of TriMatrix Memory Features (Part 2 of 2)
Stratix III Device Handbook, Volume 1
Byte-enable
Packed mode
Address clock enable
Single-port memory
Simple dual-port memory
True dual-port memory
Embedded shift register
ROM
FIFO buffer
Simple dual-port mixed
width support
True dual-port mixed width
support
Memory initialization file
(.mif)
Mixed-clock mode
Power-up condition
Register clears
Asynchronous clear on
output latch
Write/Read operation
triggering
Same-port read-during-write
Mixed-port read-during-write
ECC Support
Notes to
(1) In ROM mode, MLABs support the (depth × width) configurations of 64×8, 64×9, 64×10, 32×16, 32×18, or 32× 20.
(2) MLABs support byte-enable via emulation.
Table
Feature
4–1:
Soft IP support via Quartus II
Outputs cleared if registered,
Write: Falling clock edges
Outputs set to old data or
Read: Rising clock edges
otherwise reads memory
Outputs set to don’t care
Output registers
don’t care
contents
software
MLABs
v
v
v
v
v
v
v
v
v
—
—
—
—
—
Write and Read: Rising clock
Soft IP support via Quartus II
Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Outputs set to old or new
Outputs set to old data or
Output registers
Outputs cleared
M9K Blocks
don’t care
software
edges
data
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Write and Read: Rising clock
SDP mode or soft IP support
Built-in support in ×64 wide
Outputs set to old or new
Outputs set to old data or
© May 2009 Altera Corporation
via Quartus II software
Output registers
Outputs cleared
M144K Blocks
don’t care
edges
data
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Overview