EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 378

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

11–46
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 3 of 5)
Stratix III Device Handbook, Volume 1
nSTATUS
nSTATUS
(continued)
Pin Name
User Mode
N/A
—
Configuration
Scheme
All
—
Bi-directional
open-drain
Pin Type
—
The device drives nSTATUS low immediately after
power-up and releases it after the POR time.
During user mode and regular configuration, this pin is
pulled high by an external 10-kΩ resistor.
This pin, when driven low by Stratix III, indicates that
the device is being initialized and has encountered an
error during configuration.
Status output. If an error occurs during configuration,
nSTATUS is pulled low by the target device.
Status input. If an external source drives the nSTATUS
pin low during configuration or initialization, the target
device enters an error state.
Driving nSTATUS low after configuration and
initialization does not affect the configured device. If you
use a configuration device, driving nSTATUS low will
cause the configuration device to attempt to configure
the device, but since the device ignores transitions on
nSTATUS in user-mode, the device does not
reconfigure. To initiate a reconfiguration, nCONFIG
must be pulled low.
If you have enabled the Auto-restart configuration after
error option, the nSTATUS pin transitions from high to
low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS
pin with a minimum pulse width of 10 μs to a maximum
pulse width of 500 μs, as defined in the t
specification.
If V
could occur:
■
■
V
nSTATUS buffer to function properly, and
nSTATUS is driven low. When V
ramped up, POR trips and nSTATUS is released after
POR expires.
V
nSTATUS buffer to function properly. In this
situation, nSTATUS might appear logic high,
triggering a configuration attempt that would fail
because POR did not yet trip. When V
powered up, nSTATUS is pulled low because POR
did not yet trip. When POR trips after V
are powered up, nSTATUS is released and pulled
high. At that point, reconfiguration is triggered and
the device is configured.
CC PGM
CC PGM
CC PGM
and V
and V
and V
C CIO
C CIO
C CIO
are not fully powered up, the following
are powered high enough for the
are not powered high enough for the
Chapter 11: Configuring Stratix III Devices
Description
© March 2011 Altera Corporation
Device Configuration Pins
C CPGM
CC PD
and V
STATUS
CC PGM
and V
C CIO
and V
C CIO
are
are
C CIO