EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 417
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
IEEE Std. 1149.1 BST Circuitry (Disabling)
IEEE Std. 1149.1 BST Circuitry (Disabling)
IEEE Std. 1149.1 BST Guidelines
© July 2010
Altera Corporation
1
The IEEE Std. 1149.1 BST circuitry for Stratix III devices is enabled upon device
power-up. Because the IEEE Std. 1149.1 BST circuitry is used for BST or in-circuit
reconfiguration, you must enable the circuitry only at specific times as mentioned in,
“IEEE Std. 1149.1 BST Circuitry” on page
If you are not using the IEEE Std. 1149.1 circuitry in Stratix III, you should
permanently disable the circuitry to ensure that you do not inadvertently enable it
when it is not required.
Table 13–7
circuitry in Stratix III devices.
Table 13–7. Disabling IEEE Std. 1149.1 Circuitry
Use the following guidelines when performing boundary-scan testing with IEEE Std.
1149.1 devices:
■
Note to
(1) There is no software option to disable JTAG in Stratix III devices. The JTAG pins are dedicated.
If the “10...” pattern does not shift out of the instruction register through the TDO
pin during the first clock cycle of the SHIFT_IR state, the TAP controller did not
reach the proper state. To solve this problem, try one of the following procedures:
■
■
Do NOT use the following private instructions as they may render the device
inoperable:
11 0001 0000
00 1100 1001
11 0001 0011
11 0001 0111
You should take precautions to avoid invoking these instructions at any time.
Verify that the TAP controller has reached the SHIFT_IR state correctly. To
advance the TAP controller to the SHIFT_IR state, return to the RESET state
and send the code 01100 to the TMS pin.
Check the connections to the V
pins on the device.
Table
lists the pin connections necessary for disabling the IEEE Std. 1149.1
13–7:
JTAG Pins
TRST
TMS
TCK
TDI
TDO
(1)
CC
, GND, JTAG, and dedicated configuration
13–18.
Connection for Disabling
V
V
CC PD
CC PD
Stratix III Device Handbook, Volume 1
supply of Bank 1A
supply of Bank 1A
Leave open
GND
GND
13–19
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