EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 176

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

6–28
Stratix III Device Handbook, Volume 1
Source-Synchronous Mode for LVDS Compensation
The goal of this mode is to maintain the same data and clock timing relationship seen
at the pins at the internal SERDES capture register, except that the clock is inverted
(180-degree phase shift). Thus, this mode ideally compensates for the delay of the
LVDS clock network plus any difference in delay between these two paths:
■
■
No-Compensation Mode
In the no-compensation mode, the PLL does not compensate for any clock networks.
This mode provides better jitter performance because the clock feedback into the PFD
passes through less circuitry. Both the PLL internal- and external-clock outputs are
phase-shifted with respect to the PLL clock input.
waveform of the PLL clocks’ phase relationship in this mode.
Figure 6–25. Phase Relationship Between PLL Clocks in No Compensation Mode
Note to
(1) The PLL clock outputs will lag the PLL input clocks, depending on routing delays.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock-output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software timing analyzer reports any phase difference between
the two. In normal mode, the delay introduced by the GCLK or RCLK network is fully
compensated.
relationship in this mode.
Data pin-to-SERDES capture register
Clock input pin-to-SERDES capture register. In addition, the output counter needs
to provide the 180-degree phase shift.
Figure
External PLL Clock Outputs (1)
6–25:
Figure 6–26
Register Clock Port (1)
PLL Clock at the
PLL Reference
Clock at the
Input Pin
shows an example waveform of the PLL clocks’ phase
Phase Aligned
Chapter 6: Clock Networks and PLLs in Stratix III Devices
Figure 6–25
© July 2010 Altera Corporation
shows an example
PLLs in Stratix III Devices