EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 400

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

13–2
Table 13–1. IEEE Std. 1149.1 Pin Descriptions
Stratix III Device Handbook, Volume 1
TDI
TDO
TMS
TCK
TRST
Note to
(1) The minimum TRST pulse width to reset the JTAG TAP controller is 60 ns.
Pin
Table
(1)
13–1:
Test data input
Test data output
Test mode select
Test clock input
Test reset input
(optional)
Description
Table 13–1
The IEEE Std. 1149.1 BST circuitry requires the following registers:
■
■
■
The instruction register determines the action to be performed and the data
register to be accessed.
The bypass register is a one-bit-long data register that provides a minimum-length
serial path between TDI and TDO.
The boundary-scan register is a shift register composed of all the boundary-scan
cells of the device.
summarizes the functions of each of these pins.
Serial input pin for instructions as well as test and programming data. Signal applied
to TDI is expected to change state at the falling edge of TCK. Data is shifted in on
the rising edge of TCK.
Serial data output pin for instructions as well as test and programming data. Data is
shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted
out of the device.
Input pin that provides the control signal to determine the transitions of the test
access port (TAP) controller state machine. Transitions within the state machine
occur at the rising edge of TCK. Therefore, you must set up TMS before the rising
edge of TCK. TMS is evaluated on the rising edge of TCK. During non-JTAG
operation, Altera recommends you drive TMS high.
The clock input to the BST circuitry. Some operations occur at the rising edge, while
others occur at the falling edge.
Active-low input to asynchronously reset the boundary-scan circuit. For non-JTAG
users, you should permanently tie the pin to GND.
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
Function
IEEE Std. 1149.1 BST Architecture
© July 2010 Altera Corporation