EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 351

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
© March 2011 Altera Corporation
In configuration mode, Stratix III devices enable the serial configuration device by
driving the nCSO output pin low, which connects to the chip select (nCS) pin of the
configuration device. The Stratix III device uses the serial clock (DCLK) and serial data
output (ASDO) pins to send operation commands, read address signals, or both to the
serial configuration device. The configuration device provides data on its serial data
output (DATA) pin, which connects to the DATA0 input of the Stratix III devices.
After all configuration bits are received by the Stratix III device, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 10-kΩ resistor.
Initialization begins only after the CONF_DONE signal reaches a logic high level. All AS
configuration pins (DATA0, DCLK, nCSO, and ASDO) have weak internal pull-up
resistors that are always active. After configuration, these pins are set as input
tri-stated and are driven high by the weak internal pull-up resistors. The CONF_DONE
pin must have an external 10-kΩ pull-up resistor for the device to initialize.
In Stratix III devices, the initialization clock source is either the 10 MHz (typical)
internal oscillator (separate from the active serial internal oscillator) or the optional
CLKUSR pin. By default, the internal oscillator is the clock source for initialization. If
you use the internal oscillator, the Stratix III device has enough clock cycles for proper
initialization. You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software on the
General tab of the Device and Pin Options dialog box. When you enable the user
supplied start-up clock option, the CLKUSR pin is the initialization clock source.
Supplying a clock on CLKUSR does not affect the configuration process. When all
configuration data has been accepted and CONF_DONE goes high, CLKUSR is enabled
after 600 ns. After this time period elapses, Stratix III devices require 4,436 clock cycles
to initialize properly and enter user mode. Stratix III devices support a CLKUSR f
100 MHz.
An optional INIT_DONE pin is available, which signals the end of initialization and
the start of user-mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software on the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it will be high due to an
external 10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. When the option bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin goes low.
When initialization is complete, the INIT_DONE pin is released and pulled high. This
low-to-high transition signals that the device has entered user mode. When
initialization is complete, the device enters user mode. In user mode, the user I/O
pins no longer have weak pull-up resistors and function as assigned in your design.
If an error occurs during configuration, Stratix III devices assert the nSTATUS signal
low, indicating a data frame error, and the CONF_DONE signal stays low. If the
Auto-restart configuration after error option (available in the Quartus II software on
the General tab of the Device and Pin Options dialog box) is turned on, the Stratix III
device resets the configuration device by pulsing nCSO, releases nSTATUS after a reset
time-out period (maximum of 100 μs), and retries configuration. If this option is
turned off, the system must monitor nSTATUS for errors and then pulse nCONFIG low
for at least 2 μs to restart configuration.
Stratix III Device Handbook, Volume 1
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