EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 127

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

Chapter 5: DSP Blocks in Stratix III Devices
Operational Mode Descriptions
Two-Multiplier Adder Sum Mode
© March 2010 Altera Corporation
1
In the two-multiplier adder configuration, the DSP block can implement four 18-bit
Two-Multiplier Adders (2 Two-Multiplier Adders per half DSP block). You can
configure the adders to take the sum or difference of two multiplier outputs.
Summation or subtraction has to be selected at compile time. The Two-Multiplier
Adder function is useful for applications such as FFTs, complex FIR, and IIR filters.
Figure 5–14
The loopback mode is the other sub-feature of the two-multiplier adder mode.
Figure 5–15
the 36-bit summation result of the two multipliers and feeds back the most significant
18-bits to the input. The lower 18-bits are discarded. You have the option to disable or
zero-out the loopback data by using the dynamic zero_loopback signal. A logic 1
value on the zero_loopback signal selects the zeroed data or disables the looped
back data, while a logic 0 selects the looped back data.
The option to use the loopback mode or the general two-multiplier adder mode must
be selected at compile time.
For the Two-Multiplier Adder mode, if all the inputs are full 18-bit and unsigned, the
result will require 37 bits. As the output data width in Two-Multiplier Adder mode is
limited to 36 bits, this 37-bit output requirement is not allowed. Any other
combination that does not violate the 36-bit maximum result is permitted; for
example, two 16 × 16 signed Two-Multiplier Adders is valid.
The two-multiplier adder mode supports the round and saturation logic unit. You can
use the pipeline registers and output registers within the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
shows the DSP block configured in the two-multiplier adder mode.
shows the DSP block configured in the loopback mode. This mode takes
Stratix III Device Handbook, Volume 1
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