EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 280

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

8–32
Figure 8–16. DDR3 SDRAM Unbuffered Module Clock Topology
Figure 8–17. Stratix III Write Leveling Delay Chains and Multiplexers
Note to
(1) There is only one leveling delay chain per I/O bank with the same I/O number (for example, I/O banks 1A, 1B, and 1C). You can only have one
Stratix III Device Handbook, Volume 1
memory controller in these I/O banks when you use leveling delay chains.
Figure
DQS/DQ
8–17:
DQS/DQ
Because the data and read strobe signals are still point-to-point, special consideration
must be taken to ensure that the timing relationship between CK/CK# and DQS
signals (t
data coming back into the FPGA from the memory is also staggered in a similar way.
Stratix III FPGAs have leveling circuitry to take care of these two requirements. There
is one group of leveling circuitry per I/O bank, with the same I/O number (for
example, there is one leveling circuitry shared between I/O bank 1A, 1B, and 1C)
located in the middle of the I/O bank. These delay chains are PVT-compensated by
the same DQS delay settings as the DLL and DQS delay chains. For frequencies equal
to and above 400 MHz, the DLL uses eight delay chains such that each delay chain
generates a 45 ° delay.
The generated clock phases are distributed to every DQS logic block that is available
in the I/O bank. The delay chain taps, then feeds a multiplexer controlled by the
ALTMEMPHY megafunction to select which clock phases are to be used for that ×4 or
×8 DQS group. Each group can use a different tap output from the read-leveling and
write-leveling delay chains to compensate for the different CK/CK# delay going into
each device on the module.
Figure 8–17
Write clk
(-90
DQS/DQ
DQSS
0
)
illustrates the Stratix III write leveling circuitry.
) during a write is met at every device on the modules. Furthermore, read
DQS/DQ
CK/CK#
DQS/DQ
(Note 1)
Chapter 8: External Memory Interfaces in Stratix III Devices
Write-Leveled DQ Clock
Write-Leveled DQS Clock
DQS/DQ
Stratix III External Memory Interface Features
DQS/DQ
© March 2010 Altera Corporation
DQS/DQ
Stratix III