EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 18
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
- Current page: 18 of 456
- Download datasheet (7Mb)
xviii
Figure 7–23: Differential HSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . 7-35
Figure 7–24: LVDS I/O Standard Termination for Stratix III Devices
Figure 7–25: LVPECL AC Coupled Termination
Figure 7–26: LVPECL DC Coupled Termination
Figure 7–27: RSDS I/O Standard Termination for Stratix III Devices
Figure 7–28: Mini-LVDS I/O Standard Termination for Stratix III Devices
Figure 8–1: Package Bottom View for Stratix III Devices
Figure 8–2: External Memory Interface Data Path Overview
Figure 8–3: Number of DQS/DQ Groups per Bank in EP3SE50, EP3SL50, and EP3SL70 Devices in the
484-pin FineLine BGA Package
Figure 8–4: Number of DQS/DQ Groups per Bank in EP3SE50, EP3SL50, EP3SL70, EP3SE80, EP3SE110,
EP3SL110, EP3SL150, EP3SL200, and EP3SE260 Devices in the 780-pin FineLine BGA Package
8-9
Figure 8–5: Number of DQS/DQ Groups in EP3SE80, EP3SE110, EP3SL110, EP3SL150, EP3SL200,
EP3SE260, and EP3SL340 Devices in the 1152-pin FineLine BGA Package
Figure 8–6: Number of DQS/DQ Groups per Bank in EP3SL200, EP3SE260 and EP3SL340 Devices in the
1517-pin FineLine BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Figure 8–7: DQS/DQ Bus Mode Support per Bank in EP3SL340 Devices in the 1760-pin FineLine BGA Pack-
age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Figure 8–8: DQS Pins in Stratix III I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
Figure 8–9: Memory Clock Generation Block Diagram
Figure 8–10: DQS and CQn Pins and DQS Phase-Shift Circuitry
Figure 8–11: Stratix III DLL and I/O Bank Locations (Package Bottom View) . . . . . . . . . . . . . . . . . . . . . 8-22
Figure 8–12: Simplified Diagram of the DQS Phase Shift Circuitry
Figure 8–13: Stratix III DQS Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Figure 8–14: Example of a DQS Update Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
Figure 8–15: Avoiding a Glitch on a Non-Consecutive Read Burst Waveform . . . . . . . . . . . . . . . . . . . . . 8-31
Figure 8–16: DDR3 SDRAM Unbuffered Module Clock Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
Figure 8–17: Stratix III Write Leveling Delay Chains and Multiplexers
Figure 8–18: Stratix III Read Leveling Delay Chains and Multiplexers
Figure 8–19: Stratix III Dynamic OCT Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
Figure 8–20: Stratix III IOE Input Registers
Figure 8–21: Stratix III IOE Output and Output-Enable Path Registers
Figure 8–22: Delay Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39
Figure 8–23: Delay Chains in an I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40
Figure 8–24: Delay Chains in the DQS Input Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40
Figure 8–25: I/O Configuration Block and DQS Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41
Figure 9–1: I/O Banks in Stratix III Devices
Figure 9–2: Transmitter Block Diagram for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Figure 9–3: Transmitter in Clock Output Mode for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Figure 9–4: Serializer Bypass for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Figure 9–5: Receiver Block Diagram for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Figure 9–6: Deserializer Bypass for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Figure 9–7: Data Realignment Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Figure 9–8: DPA Clock Phase-to-Serial Data Timing Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Figure 9–9: Soft-CDR Data and Clock Path for a Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Figure 9–10: Programmable V
Figure 9–11: On-Chip Differential I/O Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Figure 9–12: PLL Block Diagram for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Figure 9–13: LVDS/DPA Clocks with Center PLLs for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Stratix III Device Handbook, Volume 1
OD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
(Note 1)
(Note
(Note 1)
(Note 1)
1), (2), (3), (4), (5),
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
(Note 1)
(Note
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
(Note
1),
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
(2)
1), (2),
(Note 1)
(Note
(Note 1)
(6)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
(Note 1)
(Note 1)
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
(Note
(3)
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . 8-20
1),
. . . . . . . . . . . . . . . . . . . . . 7-36
. . . . . . . . . . . . . . . . . . . . . . 8-3
. . . . . . . . . . . . . . . . . . . . . 8-26
(2)
. . . . . . . . . . . . . . . . . . . 8-32
. . . . . . . . . . . . . . . . . . . 8-33
. . . . . . . . . . . . . . . . . . . 8-38
1),
© March 2011 Altera Corporation
. . . . . . . . . . . . . . . . . . 7-38
. . . . . . . . . . . . . . . . 8-10
(2)
. . . . . . . . . . . . 7-39
(Note 1)
List of Figures
.
Related parts for EP3SL150F1152C2N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: