EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 142

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

5–36
Stratix III Device Handbook, Volume 1
Normally in a FIR filter, the fixed data input (from general routing and not from
cascade) is the constant that needs to be multiplied by the cascaded input. In 18-bit
mode, the DSP block has enough input registers to register the general routing signals
and the cascaded signal buses before multiplying them. This makes having eight taps
for an 18-bit cascade mode possible. Each tap can be considered a single multiplier. If
all eight multiplier inputs for the full DSP block are cascaded in a parallel scan chain,
an eight-tap FIR filter is created, as shown in
The DSP block can be concatenated to have more than eight taps by enabling the
option to output the parallel scan chain to the next (lower) DSP block. Likewise, the
output of previous (above) cascade chain is used as an input to the current block. The
first (top) multiplier in each half block will have the option to select the 18-bit cascade
chain input from the regular routing or from the previous (above) cascade chain. Also,
the last cascaded chain in each half DSP block can exit the DSP block by routing the
cascade chain after the last (fourth from top) input register to the output routing
channel, bypassing both the pipeline and output registers. This concatenation allows
the user to easily construct their desired filter length.
You can use the Four-Multiplier Adder mode with one of the inputs to each multiplier
being in a form of chained cascaded input from the previous (above) register. This is
very similar to the regular Four-Multiplier Adder with the difference being that not all
the inputs are from general routing.
For a complete FIR, the results per individual Four-Multiplier Adder can be combined
in either a tree or chained cascade manner. Using external logic and adders, you can
very easily implement a tree summation, as shown in
Figure
5–22.
Chapter 5: DSP Blocks in Stratix III Devices
Figure
© March 2010 Altera Corporation
5–22.
Application Examples