EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 224
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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7–20
OCT Support
Stratix III Device Handbook, Volume 1
1
Stratix III devices feature dynamic series and parallel on-chip termination to provide
I/O impedance matching and termination capabilities. OCT improves signal quality
over external termination by reducing parasitic, saving board space, and reducing
external component costs.
Stratix III devices support OCT R
calibration, and dynamic series and parallel termination for single-ended I/O
standards as well as OCT R
support OCT in all I/O banks by selecting one of the OCT I/O standards.
Stratix III devices support OCT R
standards if they use the same V
independently configured to support OCT R
OCT R
You cannot configure both OCT R
I/O buffer.
A pair of RUP and RDN pins are available in a given I/O bank, and are shared for
series- and parallel-calibrated termination. The RUP and RDN pins share the same V
and GND, respectively, with the I/O bank where they are located. The RUP and RDN
pins are dual-purpose I/Os, and function as regular I/Os if you do not use the
calibration circuit. When used for calibration, the RUP pin is connected to V
through an external 25-Ω ±1% or 50-Ω ±1% resistor for an OCT R
Ω , respectively; the RDN pin is connected to GND through an external 25-Ω ±1% or
50-Ω ±1% resistor for an OCT R
RUP pin is connected to V
connected to GND through an external 50-Ω±1% resistor.
On-Chip Series Termination without Calibration
Stratix III devices support driver-impedance matching to provide the I/O driver with
controlled output impedance that closely matches the impedance of the transmission
line. As a result, you can significantly reduce reflections. Stratix III devices support
OCT R
The R
typical R
strength is no longer selectable.
S
T
S
shown in
.
for single-ended I/O standards (see
S
values are 25 Ω and 50 Ω. When matching impedance is selected, current
Figure 7–8
CCIO
D
is the intrinsic impedance of the output transistors. The
for differential LVDS I/O standards. Stratix III devices
through an external 50-Ω ±1% resistor; the RDN pin is
S
CCIO
value of 25 Ω or 50 Ω , respectively. For OCT R
S
S
S
with or without calibration, OCT R
and R
and programmable current strength for the same
supply voltage. Each I/O in an I/O bank can be
T
in the same I/O bank for different I/O
Figure
S
, programmable current strength, or
7–8).
Chapter 7: Stratix III Device I/O Features
© July 2010 Altera Corporation
S
value of 25 Ω or 50
T
with
CCIO
OCT Support
T
, the
CCIO
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