EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 436

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

15–6
Error Detection Pin Description
CRC_ERROR Pin
Table 15–3. CRC_ERROR Pin Description
Stratix III Device Handbook, Volume 1
CRC_ERROR
Pin Name
f
1
I/O, output, or
open-drain
output (optional)
Depending on the type of error detection feature you choose, you will need to use
different error detection pins to monitor the data during user mode. The different
error detection pins available are described in the following sections.
Table 15–3
WYSIWYG is a design primitive that corresponds to device features and can be
directly instantiated into your RTL design.
The CRC_ERROR pin information for Stratix III devices is reported in Device Pin-Outs
on the Literature page of the Altera website (www.altera.com).
Pin Type
lists the CRC_ERROR pin.
Active high signal that indicates the error detection circuit has detected errors in
the configuration CRAM bits. This pin is optional and is used when the error
detection CRC circuit is enabled. When the error detection CRC circuit is
disabled, it is a user I/O pin.
The CRC error output, when using the WYSIWYG function, is a dedicated path to
the CRC_ERROR pin. By default, the Quartus II software sets the CRC_ERROR
pin as a dedicated output.
If CRC_ERROR is used as a dedicated output, make sure V
the pin resides meets the input voltage specification of the system receiving the
signal. Optionally, you can set this pin to be an open-drain output by enabling the
option in the Quartus II software from the Error Detection CRC tab of the
Device & Pin Options dialog box.
Using this pin as open-drain provides advantage on voltage leveling. To use this
pin as open-drain, tie the pin to V
depending on the voltage input voltage specification of the system receiving the
signal, you can tie the pull-up resistor to a different pull-up voltage.
CC PGM
Description
through a 10-kΩ resistor. Alternatively,
Chapter 15: SEU Mitigation in Stratix III Devices
© March 2010 Altera Corporation
Error Detection Pin Description
CC IO
of the bank where