DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 63

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

10.2.5 Gapped Clocks
The transmit and receive output clocks can be gapped in certain configurations. See
for the configuration settings. The gapped clocks are active during DS3 or E3 framed payload bits overhead bits
depending on which mode the device is configured for.
In the internal DS3 or E3 frame modes, the transmit gapped clock is created by the logical OR of the TCLKO and
TDEN signals creating a positive or negative clock edge for each payload bit, the receive gapped clock is created
by the logical OR of the RCLKO and RDEN signals.
When the output clock is disabled, the gapped output signal is high during clock periods if the pin is not inverted,
otherwise it will be low.
The gapped clocks are very useful when the data being clocked does not need to be aligned with any frame
structure. The data is simply clocked one bit at a time as a continuous data stream.
10.3 Reset and Power-Down
The device can be reset at a global level via the GL.CR1.RST bit or the RST pin and at the port level via the
PORT.CR1.RST bit and the port can be explicitly powered down via the PORT.CR1.PD bit. The JTAG logic is reset
using the power on reset signal from one of the LIUs as well as from the JTRST pin.
The external RST pin and the global reset bit in the global configuration register (GL.CR1.RST) are combined to
create an internal global reset signal. The global reset signal resets all the status and control registers on the chip,
except the GL.CR1.RST bit, to their default values and resets all the other flops in the global logic and port to their
Figure 10-4. Example IO Pin Clock Muxing
TSER
TCLKI
RLCLK
CLAD CLOCKS
STS-1 CLK
RX LIU CLK
DS3 CLK
E3 CLK
PIN INVERT
PIN INVERT
PIN INVERT
DELAY
TFTS
0
1
CLOCK TREE
CLOCK TREE
CLOCK TREE
INTERNAL
INTERNAL
INTERNAL
SIGNAL
SIGNAL
SIGNAL
D
SET
CLR
Q
Q
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D
D
D
D
CLR
CLR
SET
SET
SET
CLR
SET
CLR
Q
Q
Q
Q
Q
Q
Q
Q
INTERNAL
DELAY
DELAY
DELAY
SIGNAL
TFTS
RFTS
TLTS
DS3170 DS3/E3 Single-Chip Transceiver
0
1
0
1
0
1
D
D
D
SET
CLR
SET
CLR
SET
CLR
Q
Q
Q
Q
Q
Q
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
PIN INVERT
Table 10-22
RCLKO
TCLKO
TLCLK
TDEN
RSER
TPOS
and
Table 10-24