DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 32

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

TSOFO /
TDEN
RSER
RCLKO /
RGCLK
RSOFO /
RDEN
PIN NAME
TYPE
O
O
O
O
Framer Start Of Frame / Data Enable
See
TSOFO: When the port framer is configured for the DS3 or E3 framed modes and the
TSOFO pin function is selected, this signal is used to indicate the start of the DS3/E3
frame on the TSER pin. This signal pulses high three clocks before the first overhead
bit in a DS3 or E3 frame that will be input on TSER. The signal is updated on the
positive clock edge of the referenced clock pin if the clock pin signal is not inverted,
otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the TCLKI transmit clock input pins, but it can be referenced to the
TLCLK, TCLKO, RCLKO and RLCLK clock pins.
This signal can be inverted.
TDEN: When the port framer is configured for the DS3 or E3 framed modes and the
TDEN pin function is selected, this signal is used to mark the DS3/E3 frame bits on
the TSER pin. The signal goes high three clocks before the start of DS3/E3 payload
bits and goes low three clocks before the end of the DS3/E3 payload bits. The signal
is updated on the positive clock edge of the referenced clock pin if the clock pin signal
is not inverted, otherwise it is updated on the falling edge of the clock. The signal is
typically referenced to the TCLKI transmit clock input pins, but it can be referenced to
the TLCLK, TCLKO, RCLKO and RLCLK clock pins.
This signal can be inverted.
Receive Serial Data
RSER: When the port framer is configured for the DS3 or E3 framed modes, this pin
outputs the receive data signal from the LIU or receive line pins. The signal is updated
on the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is updated on the falling edge of the clock. The signal is typically
referenced to the RCLKO receive clock output pin, but it can be referenced to the
RGCLK and RLCLK clock pins.
This signal can be inverted
o
o
Receive Clock Output / Gapped Clock
See
RCLKO: When the port framer is configured for the DS3 or E3 framed modes and
RCLKO is selected, this clock output signal is active. It is the same as the internal
receive framer clock. This clock is typically used for the reference clock for the RSER,
RSOFO / RDEN signals but can also be used as the reference for the RPOS / RDAT,
RNEG / RLCV, TSOFI, TSER, TSOFO / TDEN, TPOS / TDAT and TNEG signals.
This signal can be inverted.
o
o
RGCLK: When the port is configured for DS3/E3 framed mode and RGCLK is
selected, this gated clock output signal is active. It is the same as the internal receive
framer clock gated by RDEN. This clock is typically used for the reference clock for
the RSER.
This signal can be inverted
Receive Framer Start Of Frame /Data Enable
See
RSOFO: When the port framer is configured for the DS3 or E3 framed modes and the
RSOFO pin function is enabled, this signal is used to indicate the start of the DS3/E3
frame. This signal indicates the first DS3/E3 overhead bit on the RSER pin when high.
The signal is updated on the positive clock edge of the referenced clock pin if the
clock pin signal is not inverted, otherwise it is updated on the falling edge of the clock.
The signal is typically referenced to the RCLKO receive clock output pin, but it can be
referenced to the RLCLK clock input pin.
This signal can be inverted.
RDEN: When the port framer is configured for the DS3 or E3 framed modes and the
RDEN pin function is enabled, this signal is used to indicate the DS3/E3 payload bit
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 MHz +20 ppm
E3: 34.368 MHz +20 ppm
Table 10-21.
Table 10-24.
Table 10-23.
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PIN DESCRIPTION
DS3170 DS3/E3 Single-Chip Transceiver