DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 44

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

expected. If the BURST bit is not set, each data byte will be followed by the control byte(s) for the next access.
Additionally, CS may also be de-asserted between accesses when CPHA =1. In the case, any BURST access is
terminated, and the next byte received when CS is re-asserted will be a control byte.
The following diagrams describe the functionality of the SPI port for the four combinations of SPI_CPOL and
SPI_CPHA. They indicate the clock edge that samples the data and the level of the clock during no-transfer events
(high or low). Since the SPI port of the DS3170 acts as a slave device, the master device provides the clock. The
user must configure the SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master device is
providing.
Figure 8-19. SPI Serial Port Access For Read Mode, SPI_CPOL=0, SPI_CPHA = 0
Figure 8-20. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 0
Figure 8-21. SPI Serial Port Access For Read Mode, SPI_CPOL = 0, SPI_CPHA = 1
Figure 8-22. SPI Serial Port Access For Read Mode, SPI_CPOL = 1, SPI_CPHA = 1
MOSI
MISO
MOSI
MISO
MOSI
MISO
MOSI
MISO
SCK
SCK
SCK
SCK
CS*
CS*
CS*
CS*
MSB
MSB
MSB
MSB
1
1
1
1
A13
A13
A13
A13
A12
A12
A12
A12
A11
A11
A11
A11
A10
A10
A10
A10
A9
A9
A9
A9
A8
A8
A8
A8
LSB
LSB
LSB
LSB
A7
A7
A7
A7
MSB
MSB
MSB
MSB
A6
A6
A6
A6
A5
A5
A5
A5
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A4
A4
A4
A4
A3
A3
A3
A3
A2
A2
A2
A2
A1
A1
A1
A1
A0
A0
A0
A0
DS3170 DS3/E3 Single-Chip Transceiver
LSB
LSB
LSB
LSB
B
B
B
B
MSB
MSB
MSB
MSB
D7
D7
D7
D7
D6
D6
D6
D6
D5
D5
D5
D5
D4
D4
D4
D4
D3
D3
D3
D3
D2
D2
D2
D2
D1
D1
D1
D1
LSB
LSB
LSB
LSB
D0
D0
D0
D0