DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 165

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Transmit FEAC Idle Interrupt Enable (TFIIE) – This bit enables an interrupt if the TFIL bit is set and the bit
in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
12.7.2 FEAC Receive Side Register Map
The receive side utilizes five registers.
Table 12-19. FEAC Receive Side Register Map
12.7.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Receive FEAC Reset (RFR) –When 0, the Receive FEAC Processor and Receive FEAC FIFO will resume
normal operations. When 1, the Receive FEAC controller is reset. The FEAC FIFO is emptied, any transfer in
progress is halted, and all incoming data is discarded.
Address
0DCh
0DAh
0DEh
0D0h
0D2h
0D4h
0D6h
0D8h
0 = interrupt disabled
1 = interrupt enabled
15
15
FEAC.RCR
FEAC.RSR
FEAC.RSRL
FEAC.RSRIE
FEAC.RFDR
--
--
--
--
0
7
0
0
7
0
Register
--
--
--
14
14
--
--
--
--
0
6
0
0
6
0
FEAC Receive Control Register
Unused
FEAC Receive Status Register
FEAC Receive Status Register Latched
FEAC Receive Status Register Interrupt Enable
Unused
FEAC Receive FIFO Data Register
Unused
Register Description
FEAC.TSRIE
FEAC Transmit Status Register Interrupt Enable
0C8h
FEAC.RCR
FEAC Receive Control Register
0D0h
13
13
--
--
--
--
0
5
0
0
5
0
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12
12
--
--
--
--
0
4
0
0
4
0
11
11
--
--
--
--
0
3
0
1
3
0
DS3170 DS3/E3 Single-Chip Transceiver
10
10
--
--
--
--
0
2
0
0
2
0
--
--
--
--
9
0
1
0
9
0
1
0
TFIIE
RFR
--
--
8
0
0
0
8
0
0
0