DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 54

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

The clear on write mode expects the user to use the following protocol:
This protocol is useful when multiple uncoordinated software tasks access the same latched register. Each task
should only clear the bits with which it is concerned; the other tasks will clear the bits with which they are
concerned.
The clear on read mode is simpler since the bits that were read as being set will be cleared automatically. This
method will work well in a software system where multiple tasks do not read the same latched status register. The
latched status register bits in clear on read mode are carefully designed not to miss events that occur while a
register is being read when the latched bit has not already been set. Refer to
10.1.7 Interrupt and Pin Modes
The interrupt (INT) pin is configurable to drive high or high impedance when inactive. The GL.CR1.INTM bit
controls the pin configuration. If it is set, the INT pin will drive high when inactive. After a reset, the INT pin will be in
high impedance mode until an interrupt source is active and enabled to drive the interrupt pin.
10.1.8 Interrupt Structure
The interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. The
status bits in the global status (GL.SR) and global status latched register (GL.SRL) are read to determine if the
interrupt source is a global event, a global performance monitor update or whether it came from the port. If the
interrupt event came from the port then the port status register (PORT.SR) and port status register latched
(PORT.SRL) can be read to determine if the interrupt source is a common port event like the performance monitor
update or LIU or whether it came from the DS3/E3 Framers, BERT, HDLC, FEAC or Trail Trace status registers. If
the interrupt came from the DS3/E3 Framers, BERT, HDLC, FEAC or Trail Trace status registers, then those
registers will need to be read to determine the event that caused the interrupt.
The source of an interrupt can be determined by reading three status registers: the global, port and block status
registers.
When a mode is not enabled, then interrupts from that source will not occur. For example, if E3 framing mode is
enabled, an interrupt source that is defined in DS3 framing, but not in E3 framing, cannot create a new interrupt.
Note that when modes are changed, the latched status bits of the new mode, as well as any other mode, may get
set. If the data path reset is set during or after the mode change, the latched status bits will be automatically
cleared. If the data path reset is not used to clear the latched status bits, then the registers must be cleared by
reading or writing to them based on the register clear method selected.
1. Read the latched status register
2. Write to the registers with the bits set that need to be cleared.
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DS3170 DS3/E3 Single-Chip Transceiver
Figure 8-33
and
Figure 8-34.