DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 29

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

RPOS /
RDAT
RNEG /
RLCV
TOH
TOHEN
PIN NAME
TYPE
Iad
Iad
I
I
Receive Positive AMI / Data
RPOS: When the port line is configured for B3ZS, HDB3 or AMI mode and the LIU is
disabled, a high on this pin indicates that a positive pulse has been detected using an
external LIU. The signal is sampled on the positive clock edge of the referenced clock
pin if the clock pin signal is not inverted, otherwise it is sampled on the falling edge of
the clock. The signal is typically referenced to the RLCLK line clock input pins, but it
can be referenced to the RCLKO output pins.
This input signal can be inverted.
RDAT: When the port line interface is configured for UNI mode, the un-encoded
receive signal is input on this pin. The signal is sampled on the positive clock edge of
the referenced clock pin if the clock pin signal is not inverted, otherwise it is sampled
on the falling edge of the clock. The signal is typically referenced to the RLCLK line
clock input pins, but it can be referenced to the RCLK output pins.
This input signal can be inverted.
o
o
Receive Negative AMI / Line Code Violation / Line OH Mask input
RNEG: When the port line is configured for B3ZS, HDB3 or AMI mode and the LIU is
disabled, a high on this pin indicates that a negative pulse has been detected using
an external LIU. The signal is sampled on the positive clock edge of the referenced
clock pin if the clock pin signal is not inverted, otherwise it is sampled on the falling
edge of the clock. The signal is typically referenced to the RLCLK line clock input
pins, but it can be referenced to the RCLKO output pins.
This input signal can be inverted.
o
o
RLCV: When the port line interface is configured for UNI mode, the BPV counter in
the encoder/decoder block is incremented each clock when this signal is high. The
signal is sampled on the positive clock edge of the referenced clock pin if the clock
pin signal is not inverted, otherwise it is sampled on the falling edge of the clock. The
signal is typically referenced to the RLCLK line clock input pins, but it can be
referenced to the RCLKO output pins.
This input signal can be inverted.
Transmit Overhead
TOH: When the port framer is configured for one of the DS3 or E3 framing modes,
this signal will be used to over-write the DS3 or E3 framing overhead bits when
TOHEN is active. In T3 mode, the X-bits, P-bits, M-bits, F-bits, and C-bits are input. In
G.751 E3 mode, all of the FAS, RAI, and National Use bits are input. In G.832 E3
mode, all of the FA1, FA2, EM, TR, MA, NR, and GC bytes are input. The TOHSOF
signal marks the start of the framing bit sequence. This signal is sampled at the same
time as the TOHCLK signal transitions high to low.
This signal can be inverted.
Transmit Overhead Enable / Start Of Frame Input
TOHEN: When the port framer is configured for one of the DS3 or E3 framing modes,
this signal will be used the determine which DS3 or E3 framing overhead bits to over-
write with the signal on the TOH pin. The TOHSOF signal marks the start of the
framing bit sequence. This signal is sampled at the same time as the TOHCLK signal
transitions high to low.
This signal can be inverted.
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3/E3 Overhead Interface
29 of 230
PIN DESCRIPTION
DS3170 DS3/E3 Single-Chip Transceiver