DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 108

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

10.11 BERT
10.11.1 General Description
The BERT is a software programmable test pattern generator and monitor capable of meeting most error
performance requirements for digital transmission equipment. It will generate and synchronize to pseudo-random
patterns with a generation polynomial of the form x
repetitive patterns of any length up to 32 bits.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream.
The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern
payload for the programmable test pattern. See
device.
Figure 10-27. BERT Block Diagram
10.11.2 Features
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•
•
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10.11.3 Configuration and Monitoring
Set PORT.CR1.BENA = 1 to enable the BERT. The BERT must be enabled before the pattern is loaded for the
pattern load operation to take affect.
The following tables show how to configure the on-board BERT to send and receive common patterns.
Clock Rate
Programmable PRBS pattern – The Pseudo Random Bit Sequence (PRBS) polynomial (x
are programmable (length n = 1 to 32, tap y = 1 to n - 1, and seed = 0 to 2
Programmable repetitive pattern – The repetitive pattern length and pattern are programmable (the length n
= 1 to 32 and pattern = 0 to 2
24-bit error count and 32-bit bit count registers
Programmable bit error insertion – Errors can be inserted individually, on a pin transition, or at a specific
rate. The rate 1/10
Pattern synchronization at a 10
random Bit Error Rate (BER) of 10
Receive
Transmit
DS3/E3
DS3/E3
Adapter
LIU
LIU
Encoder
Decoder
B3ZS/
B3ZS/
HDB3
HDB3
n
is programmable (n = 1 to 7).
TUA1
TAIS
n
- 1).
IEEE P1149.1
JTAG Test
Access Port
FEAC
-3
-3
.
BER – Pattern synchronization will be achieved even in the presence of a
DS3 / E3
Framer
DS3 / E3
Transmit
Receive
Formatter
Buffer
Trace
Trail
HDLC
Figure 10-27
n
108 of 230
+ x
GEN
UA1
y
+ 1, where n and y can take on values from 1 to 32 and to
for the location of the BERT Block within the DS3170
DS3170 DS3/E3 Single-Chip Transceiver
n
RX BERT
TX BERT
- 1).
Microprocessor
Interface
n
+ x
y
+ 1) and seed