DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 176

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause an error to be inserted.
12.9.2 Receive DS3 Register Map
The receive DS3 utilizes eleven registers. Two registers are shared for C-Bit and M23 DS3 modes. The M23 DS3
mode does not use the RFEBER or RCPECR count registers.
Table 12-23. Receive DS3 Framer Register Map
12.9.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 14: C-bit Overhead Masking Disable (COVHD) – When 0, the C-bit positions will be marked as overhead
(RDEN=0). When 1, the C-bit positions will be marked as data (RDEN=1). This bit is ignored in C-bit DS3 mode or
when the ROMD bit is set to one.
Bit 13: Multiframe Alignment OOF Disable (MAOD) – When 0, an OOF condition is declared whenever an
OOMF or SEF condition is declared. When 1, an OOF condition is declared only when an SEF condition is
declared.
Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled.
When 1, manual downstream AIS insertion is enabled.
Address
12Ah
12Ch
12Eh
13Ah
13Ch
13Eh
120h
122h
124h
126h
128h
130h
132h
134h
136h
138h
Reserved
RAILE
15
T3.RCR
T3.RSR1
T3.RSR2
T3.RSRL1
T3.RSRL2
T3.RSRIE1
T3.RSRIE2
T3.RFECR
T3.RPECR
T3.RFBECR
T3.RCPECR
0
7
0
Register
--
--
--
--
--
COVHD
RAILD
14
0
6
0
T3 Receive Control Register
Reserved
T3 Receive Status Register #1
T3 Receive Status Register #2
T3 Receive Status Register Latched #1
T3 Receive Status Register Latched #2
T3 Receive Status Register Interrupt Enable #1
T3 Receive Status Register Interrupt Enable #2
Reserved
Reserved
T3 Receive Framing Error Count Register
T3 Receive P-bit Parity Error Count Register
T3 Receive Far-End Block Error Count Register
T3 Receive C-bit Parity Error Count Register
Unused
Unused
Register Description
T3.RCR
T3 Receive Control Register
120h
RAIOD
MAOD
13
0
5
0
176 of 230
MDAISI
RAIAD
12
0
4
0
ROMD
AAISD
11
0
3
0
DS3170 DS3/E3 Single-Chip Transceiver
ECC
LIP1
10
0
2
0
FECC1
LIP0
9
0
1
0
FRSYNC
FECC0
8
0
0
0