DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 141

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 9: Port Status Register Interrupt Status (PSR) This bit is set when any of the latched status register bits, that
are enabled for interrupt, in the PORT.SRL register are set. The interrupt pin will be driven when this bit is set and
the GL.ISRIE.PISRIE bit is set.
bits, that are enabled for interrupt, in the B3ZS/HDB3 Line Encoder/Decoder block are set. The interrupt pin will be
driven when this bit is set and the GL.ISRIE.PISRIE bit is set.
Bit 7: Trail Trace Status Register Interrupt Status (TTSR) This bit is set when any of the latched status register
bits, that are enabled for interrupt, in the trail trace block are set. The interrupt pin will be driven when this bit is set
and the GL.ISRIE.PISRIE bit is set.
Bit 6: FEAC Status Register Interrupt Status (FSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the FEAC block are set. The interrupt pin will be driven when this bit is set and the
GL.ISRIE.PISRIE bit is set.
Bit 5: HDLC Status Register Interrupt Status (HSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the HDLC block are set. The interrupt pin will be driven when this bit is set and the
GL.ISRIE.PISRIE bit is set.
Bit 4: BERT Status Register Interrupt Status (BSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the BERT block are set. The interrupt pin will be driven when this bit is set and the
GL.ISRIE.PISRIE bit is set.
Bit 0: Framer Status Register Interrupt Status (FMSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the active DS3 or E3 framer block are set. The interrupt pin will be driven when this
bit is set and the GL.ISRIE.PISRIE bit is set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 2: Transmit Driver Monitor Status (TDM) This bits indicates the status of the transmit monitor circuit in the
transmit LIU.
Bit 8: Line Code Status Register Interrupt Status (LCSR) This bit is set when any of the latched status register
0 = Transmit output not over loaded
1 = Transmit signal is overloaded
TTSR
15
15
--
--
--
7
7
FSR
14
14
--
--
--
6
6
PORT.ISR
Port Interrupt Status Register
050h
PORT.SR
Port Status Register
052h
HSR
13
13
--
--
--
5
5
141 of 230
BSR
12
12
--
--
--
4
4
RESERVED
11
11
--
--
--
3
3
DS3170 DS3/E3 Single-Chip Transceiver
RESERVED
TDM
10
10
--
--
2
2
RESERVED
RLOL
PSR
--
9
1
9
1
FMSR
LCSR
PMS
--
8
0
8
0