DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 191

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

12.9.5 Transmit G.832 E3 Register Map
The transmit G.832 E3 utilizes four registers.
Table 12-26. Transmit G.832 E3 Framer Register Map
12.9.5.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 10: Transmit GC Byte Control (TGCC) – When 0, the GC byte is inserted from the transmit HDLC controller .
When 1, the GC byte is inserted from the GC byte register.
Note: If bit TGCC is 0 and TNRC[1:0] is 01, both the GC byte and NR byte will carry the same transmit HDLC
controller (eight bits per frame period), however, the GC byte and NR byte in the same frame may or may not be
equal.
Bits 9 to 8: Transmit NR Byte Control (TNRC[1:0]) – These two bits control the source of the NR byte.
Note: If TNRC[1:0] is 01 and TGCC is 0, both the NR byte and GC byte will carry the same transmit HDLC
controller (eight bits per frame period), however, the NR byte and GC byte in the same frame may or may not be
equal.
Bit 5: Transmit REI Error (TFEBE) – When automatic REI generation is defeated (AFEBED = 1), this bit is
inserted into the second bit of the MA byte.
Bit 4: Automatic REI Defeat (AFEBED) – When 0, the REI is automatically generated based upon the transmit
remote error indication (TREI) signal. When 1, the REI is inserted from the register bit TFEBE.
Bit 3: Transmit RDI Alarm (TRDI) – When automatic RDI generation is defeated (ARDID = 1), this bit is inserted
into the first bit of the MA byte.
Bit 2: Automatic RDI Defeat (ARDID) – When 0, the RDI is automatically generated based upon the received E3
alarms. When 1, the RDI is inserted from the register bit TRDI.
Bit 1: Transmit Frame Generation Disabled (TFGD) –
Address
11Ah
11Ch
11Eh
118h
00 = all ones.
01 = transmit from the HDLC controller.
10 = transmit from the FEAC controller.
11 = NR byte register.
0 = Transmit Frame Generation is enabled
Reserved
15
E3G832.TCR
E3G832.TEIR
E3G832.TMABR
E3G832.TNGBR
--
0
7
0
Register
14
--
--
0
6
0
E3G832.TCR
E3 G.832 Transmit Control Register
118h
E3 G.832 Transmit Control Register
E3 G.832 Transmit Error Insertion Register
E3 G.832 Transmit MA Byte Register
E3 G.832 Transmit NR and GC Byte Register
Register Description
TFEBE
13
--
0
5
0
Reserved
AFEBED
191 of 230
12
0
4
0
Reserved
TRDI
11
0
3
0
DS3170 DS3/E3 Single-Chip Transceiver
ARDID
TGCC
10
0
2
0
TNRC1
TFGD
9
0
1
0
TNRC0
TAIS
8
0
0
0