DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 171

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 2: Receive Trail Trace Identifier Mismatch (RTIM)
Bit 1: Receive Trail Trace Identifier Unstable (RTIU)
Bit 0: Receive Trail Trace Identifier Idle (RIDL)
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 3: Receive Trail Trace Identifier Change Latched (RTICL) – This bit is set when the receive trail trace
identifier is updated.
Bit 2: Receive Trail Trace Identifier Mismatch Latched (RTIML) – This bit is set when the TT.RSR.RTIM bit
transitions from 0 to 1.
Bit 1: Receive Trail Trace Identifier Unstable Latched (RTIUL) – This bit is set when the TT.RSR.RTIU bit
transitions from 0 to 1.
Bit 0: Receive Trail Trace Identifier Idle Latched (RIDLL) – This bit is set when the TT.RSR.RIDL bit transitions
from 0 to 1.
0 = Received and expected trail trace identifiers match.
1 = Received and expected trail trace identifiers do not match; trail trace identifier
mismatch (TIM) declared.
0 = Received trail trace identifier is not unstable
1 = Received trail trace identifier is in an unstable condition (TIU); TIU is declared when eight
consecutive trail trace identifiers are received that do not match either the receive trail trace
identifier or the previously stored current trail trace identifier.
0 = Received trail trace identifier is not in idle condition.
1 = Received trail trace identifier is in idle condition. Idle condition is declared upon the reception
of an all zeros trail trace identifier five consecutive times.
15
15
--
--
--
--
7
7
14
14
--
--
--
--
6
6
TT.RSR
Trail Trace Receive Status Register
0F4h
TT.RSRL
Trail Trace Receive Status Register Latched
0F6h
13
13
--
--
--
--
5
5
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12
12
--
--
--
--
4
4
RTICL
11
11
--
--
--
3
3
DS3170 DS3/E3 Single-Chip Transceiver
RTIML
RTIM
10
10
--
--
2
2
RTIUL
RTIU
--
--
9
1
9
1
RIDLL
RIDL
--
--
8
0
8
0