DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 197

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 13: Timing Source Indication Change Latched (TIL) – This bit is set when the TI[3:0] bits change state.
Bit 12: Receive Payload Type Unstable Latched (RPTUL) – This bit is set when the RPTU bit transitions from
zero to one.
Bit 11: Receive Payload Type Mismatch Latched (RPTML) – This bit is set when the RPTM bit transitions from
zero to one.
Bit 10: Receive Payload Type Change Latched (RPTL) – This bit is set when the RPT[2:0] bits change state.
Bit 8: Receive Unframed All 1’s Change Latched (RUA1L) – This bit is set when the RUA1 bit changes state.
Bit 7: GC Byte Change Latched (GCL) – This bit is set when the RGC byte changes state.
Bit 6: NR Byte Change Latched (NRL) – This bit is set when the RNR byte changes state.
Bit 5: Change Of Frame Alignment Latched (COFAL) – This bit is set when the data path frame counters are
updated with a new frame alignment that is different from the previous frame alignment.
Bit 4: Loss Of Frame Change Latched (LOFL) – This bit is set when the LOF bit changes state.
Bit 3: Remote Defect Indication Change Latched (RDIL) – This bit is set when the RDI bit changes state.
Bit 2: Alarm Indication Signal Change Latched (AISL) – This bit is set when the AIS bit changes state.
Bit 1: Out Of Frame Change Latched (OOFL) – This bit is set when the OOF bit changes state.
Bit 0: Loss Of Signal Change Latched (LOSL) – This bit is set when the LOS bit changes state.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 10: Remote Error Indication Latched (FBEL) – This bit is set when a remote error indication is detected.
Bit 9: Parity Error Latched (PEL) – This bit is set when a BIP-8 parity error is detected.
Bit 8: Framing Error Latched (FEL) – This bit is set when a framing error is detected.
Bit 2: Remote Error Indication Count Latched (FBECL) – This bit is set when the FBEC bit transitions from zero
to one.
Bit 1: Parity Error Count Latched (PECL) – This bit is set when the PEC bit transitions from zero to one.
Bit 0: Framing Error Count Latched (FECL) – This bit is set when the FEC bit transitions from zero to one.
Reserved
GCL
15
15
--
--
7
7
NRL
14
14
--
--
--
6
6
E3G832.RSRL1
E3 G.832 Receive Status Register Latched #1
128h
E3G832.RSRL2
E3 G.832 Receive Status Register Latched #2
12Ah
COFAL
TIL
13
13
--
--
5
5
197 of 230
RPTUL
LOFL
12
12
--
--
4
4
Reserved
Reserved
RPTML
RDIL
11
11
3
3
DS3170 DS3/E3 Single-Chip Transceiver
FBECL
RPTL
FBEL
AISL
10
10
2
2
Reserved
OOFL
PECL
PEL
9
1
9
1
RUA1L
LOSL
FECL
FEL
8
0
8
0