DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 187

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

Bits 9 to 8: Framing Error Count Control (FECC[1:0]) – These two bits control the type of framing error events
that are counted.
Bit 7: Receive Alarm Indication on LOF Enable (RAILE) – When 0, an LOF condition does not affect the receive
alarm indication signal (RAI). When 1, an LOF condition will cause the transmit E3 A bit to be set to one if transmit
automatic RAI is enabled.
Bit 6: Receive Alarm Indication on LOS Disable (RAILD) – When 0, an LOS condition will cause the transmit E3
A bit to be set to one if transmit automatic RAI is enabled. When 1, an LOS condition does not affect the RAI
signal.
Bit 5: Receive Alarm Indication on OOF Disable (RAIOD) – When 0, an OOF condition will cause the transmit
E3 A bit to be set to one if transmit automatic RAI is enabled. When 1, an OOF condition does not affect the RAI
signal.
Bit 4: Receive Alarm Indication on AIS Disable (RAIAD) – When 0, an AIS condition will cause the transmit E3
A bit to be set to one if transmit automatic RAI is enabled. When 1, an AIS condition does not affect the RAI signal.
Bit 3: Receive Overhead Masking Disable (ROMD) – When 0, the E3 overhead positions in the outgoing E3
payload will be marked as overhead by RDEN. When 1, the E3 overhead positions in the outgoing E3 payload will
be marked as data by RDEN.
Bits 2 to 1: LOF Integration Period (LIP[1:0]) – These two bits determine the OOF integration period for
declaring LOF.
Bit 0: Force Framer Resynchronization (FRSYNC) – A 0 to 1 transition forces an OOF condition at the FAS
check. This bit must be cleared and set to one again to force another resynchronization. Note: The OOF condition
is created by failing the most recent four data path FAS checks.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 8: Receive Unframed All 1’s (RUA1) – When 0, the receive frame processor is not in a receive unframed all
1’s (RUA1) condition. When 1, the receive frame processor is in an RUA1 condition.
Bit 7: Receive A Bit (RAB) – This bit is the integrated A bit extracted from the E3 frame.
Bit 6: Receive N Bit (RNB) – This bit is the integrated N bit extracted from the E3 frame.
Bit 4: Loss Of Frame (LOF) – When 0, the receive frame processor is not in a loss of frame (LOF) condition.
When 1, the receive frame processor is in an LOF condition.
Bit 3: Remote Alarm Indication (RDI) – This bit indicates the current state of the remote alarm indication (RDI).
Bit 2: Alarm Indication Signal (AIS) – When 0, the receive frame processor is not in an alarm indication signal
(AIS) condition. When 1, the receive frame processor is in an AIS condition.
00 = count OOF occurrences (counted regardless of the setting of the ECC bit)..
01 = count each bit error in the FAS (up to 10 per frame).
10 = count frame alignment signal (FAS) errors (up to one per frame).
11 = reserved
00 = OOF is integrated for 3 ms before declaring LOF
01 = OOF is integrated for 2 ms before declaring LOF.
10 = OOF is integrated for 1 ms before declaring LOF
11 = LOF is declared at the same time as OOF
Reserved
RAB
15
7
Reserved
RNB
14
6
E3G751.RSR1
E3 G.751 Receive Status Register #1
124h
13
--
--
5
Reserved
187 of 230
LOF
12
4
Reserved
RDI
11
3
DS3170 DS3/E3 Single-Chip Transceiver
Reserved
AIS
10
2
Reserved
OOF
9
1
RUA1
LOS
8
0