DS3170 Maxim Integrated Products, DS3170 Datasheet
DS3170
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DS3170 Summary of contents
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... Rev 2; 3/11 GENERAL DESCRIPTION The DS3170 combines a DS3/E3 framer and an LIU (single-chip transceiver) to interface to a DS3/E3 physical copper line. APPLICATIONS Access Concentrators Multiservice Access Platforms (MSAPs) Routers and Switches SONET/SDH ADM Multiservice Protocol Platform (MSPPs) SONET/SDH Muxes PBXs Test Equipment ...
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... Line Clock Modes ........................................................................................................................... 55 10.2.2 Sources of Clock Output Pin Signals ............................................................................................... 57 TABLE OF CONTENTS .............................................................................................................. 13 ................................................................................................................ 13 F ....................................................................................................... 13 EATURES F ................................................................................................ 14 EATURES ............................................................................................................ 14 EATURES ............................................................................................................. 14 ................................................................................................................ 14 ................................................................................................................ 14 .............................................................................................................. 15 (BERT) F ............................................................................................ 15 EATURES F ................................................................................................. 15 EATURES I (SPI) F ............................................................................. 15 NTERFACE EATURES ..................................................................................................................... 18 ................................................................................................................. 20 ODE ........................................................................................................... 21 ODE ...................................................................................................... 22 ODE .................................................................................................................... 23 ................................................................................................................ 24 ODE ........................................................................................................................ 25 .................................................................................................................... 27 .................................................................................................................. 52 .................................................................................................................... 53 ) ........................................................................................................................ 230 DS3170 DS3/E3 Single-Chip Transceiver ...
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... Features ....................................................................................................................................... 103 10.9.3 Functional Description ................................................................................................................... 103 10. ....................................................................................................................... 104 INE NCODER ECODER 10.10.1 General Description ...................................................................................................................... 104 10.10.2 Features ....................................................................................................................................... 105 10.10.3 B3ZS/HDB3 Encoder .................................................................................................................... 105 10.10.4 Transmit Line Interface ................................................................................................................. 105 10.10.5 Receive Line Interface .................................................................................................................. 106 10.10.6 B3ZS/HDB3 Decoder .................................................................................................................... 106 ................................................................................................................. 79 ............................................................................................................... 230 DS3170 DS3/E3 Single-Chip Transceiver ...
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... JTAG ID C ................................................................................................................................... 206 ODES 13.5 JTAG F T UNCTIONAL IMING 13 ................................................................................................................................................ 207 INS 14 PIN CONFIGURATIONS 15 DC ELECTRICAL CHARACTERISTICS 16 AC TIMING CHARACTERISTICS .................................................................................................................... 112 /D ................................................................................................... 151 ECODER .......................................................................... 203 TATE ACHINE ESCRIPTION I ................................................................................... 205 NSTRUCTIONS ..................................................................................................................... 207 4 of 230 DS3170 DS3/E3 Single-Chip Transceiver 117 119 202 208 211 213 ...
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... ITTER HARACTERISTICS 16.5 LIU NTERFACE HARACTERISTICS 16.5.1 Waveform Templates .................................................................................................................... 222 16.5.2 LIU Input/Output Characteristics.................................................................................................... 225 16.6 JTAG NTERFACE HARACTERISTICS 17 PACKAGE INFORMATION 18 THERMAL INFORMATION 19 REVISION HISTORY ............................................................................................. 215 HARACTERISTICS .................................................................................................. 216 ................................................................................................ 217 ............................................................................................................ 222 ..................................................................................................... 222 ................................................................................................. 227 5 of 230 DS3170 DS3/E3 Single-Chip Transceiver 228 229 230 ...
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... Figure 2-1. LIU External Connections for the DS3/E3 Port of DS3170 .................................................................. 10 Figure 2-2. Block Diagram ................................................................................................................................... 11 Figure 3-1. DS3/E3 Line Card .............................................................................................................................. 12 Figure 7-1. DS3/E3 Framed LIU Mode ................................................................................................................. 19 Figure 7-2. DS3/E3 Unframed LIU Mode .............................................................................................................. 20 Figure 7-3. DS3/E3 Framed POS/NEG Mode ....................................................................................................... 21 Figure 7-4. DS3/E3 Unframed POS/NEG Mode ................................................................................................... 22 Figure 7-5 ...
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... Figure 13-2. JTAG TAP Controller State Machine .............................................................................................. 203 Figure 13-3. JTAG Functional Timing ................................................................................................................. 207 Figure 14-1. DS3170 Pin Assignments—100-Ball CSBGA (Top View) ................................................................ 210 Figure 16-1. Clock Period and Duty Cycle Definitions ......................................................................................... 213 Figure 16-2. Rise Time, Fall Time, and Jitter Definitions ..................................................................................... 213 Figure 16-3 ...
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... Table 5-1. Standards Compliance ........................................................................................................................ 16 Table 8-1. DS3170 Short Pin Descriptions ........................................................................................................... 25 Table 8-2. Detailed Pin Descriptions .................................................................................................................... 27 Table 9-1. Configuration of Port Register Settings ................................................................................................ 52 Table 10-1. LIU Enable Table .............................................................................................................................. 57 Table 10-2. All Possible Clock Sources Based on Mode and Loopback ................................................................ 57 Table 10-3. Source Selection of TLCLK Clock Signal ........................................................................................... 58 Table 10-4 ...
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... Table 12-27. Receive G.832 E3 Framer Register Map ....................................................................................... 194 Table 13-1. JTAG Instruction Codes .................................................................................................................. 205 Table 13-2. JTAG ID Codes ............................................................................................................................... 206 Table 14-1. DS3170 Pin Assignments for 100-Ball CSBGA (Sorted by Signal Name) ......................................... 208 Table 14-2. DS3170 Pin Assignments for 100-Ball CSBGA (Sorted by Ball #) .................................................... 209 Table 15-1. Recommended DC Operating Conditions ........................................................................................ 211 Table 15-2 ...
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... DETAILED DESCRIPTION The DS3170 is a software-configured, DS3/E3, single-chip transceiver (SCT). The line interface unit (LIU) has independent receive and transmit paths. The receiver LIU block performs clock and data recovery from a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal, and can be bypassed for direct clock and data input. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The transmitter LIU drives standard pulse-shape waveforms onto 75Ω ...
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... HDB3 Formatter Encoder Trail FEAC Trace HDLC Buffer DS3 / E3 B3ZS/ Receive HDB3 Framer Decoder Serial or Parallel uP Inteface 11 of 230 DS3170 DS3/E3 Single-Chip Transceiver TCLKO/TGCLK TSOFO/TDEN TCLKI TSER TSOFI TX BERT RX BERT RSER RCLKO/RGCLK RSOFO/RDEN UA1 IEEE P1149.1 GEN JTAG Test Access Port ...
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... PBXs • Digital Cross Connect • PDH Multiplexer/Demultiplexer • Test Equipment • Integrated Access Device (IAD) Figure 3-1 show s a DS3170 application. Figure 3-1. DS3/E3 Line Card T3/E3 Line Card (#1) DS3170 T3/E3 DS3/E3 Trans- Line formers T3/E3 Line Card (#n) DS3170 ...
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... FEATURE DETAILS The following sections describe the features provided by the DS3170 SCT. 4.1 Global Features Supports the following transmission formats: C-Bit DS3 M23 DS3 G.751 E3 G.832 E3 All controls and status fields are software accessible over either an 8/16-bit microprocessor port or a slave serial bus communication port Mbps (SPI) ...
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... Receive FEAC automatically validates incoming codewords and stores them in a 4-codeword FIFO Transmit FEAC can be configured to send one codeword, one codeword continuously, or two different codewords back-to-back to send DS3 Line Loopback commands Terminates the FEAC channel in DS3 C-Bit Parity mode or the Sn bit in E3 mode DS3170 DS3/E3 Single-Chip Transceiver 14 of 230 ...
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... Standard JTAG instructions: SAMPLE/PRELOAD, BYPASS, EXTEST, CLAMP, HIGHZ, IDCODE Custom JTAG instructions to use RAM BIST RAM BIST on all internal RAM HIZ pin to force all digital output and inout pins into HIZ TEST pin for manufacturing scan test modes DS3170 DS3/E3 Single-Chip Transceiver 15 of 230 ...
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... Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 2, GR-499-CORE December 1998 Generic Digital Transmission Surveillance, Issue 1, November 1994 GR-820-CORE IEEE IEEE Std 1149- IEEE Standard Test Access Port and Boundary-Scan Architecture, (Includes IEEE Std 1990 1149-1993) October 21, 1993 DS3170 DS3/E3 Single-Chip Transceiver SPECIFICATION TITLE 16 of 230 ...
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... FRM—Frame Mode • FSCT—Framer Single-Chip Transceiver Mode • HDLC—High-Level Data-Link Control • Packet—HDLC Packet • SCT—Single-Chip Transceiver (Framer and LIU) • SCT Mode—DS3/E3 Framer and LIU • Unchannelized—See Clear Channel DS3170 DS3/E3 Single-Chip Transceiver 17 of 230 ...
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... E3 G.751 Framed 010 E3 G.832 Framed 011 LIU MODE LM[2:0] JA Off, B3ZS or HDB3 001 JA RX, B3ZS or HDB3 010 JA TX, B3ZS or HDB3 011 JA Off, AMI 001 JA RX, AMI 010 JA TX, AMI 011 TLEN TZSD & RZSD PORT.CR2 230 DS3170 DS3/E3 Single-Chip Transceiver ...
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... HDB3 Formatter Encoder Trail FEAC Trace HDLC Buffer DS3 / E3 B3ZS/ Receive HDB3 Framer Decoder Serial or Parallel uP Inteface 19 of 230 DS3170 DS3/E3 Single-Chip Transceiver TCLKO/TGCLK TSOFO/TDEN TCLKI TSER TSOFI TX BERT RX BERT RSER RCLKO/RGCLK RSOFO/RDEN UA1 IEEE P1149.1 GEN JTAG Test Access Port ...
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... MOSI, and MISO) TLEN TZSD & RZSD PORT.CR2 TAIS TUA1 B3ZS/ HDB3 Encoder B3ZS/ HDB3 Decoder Serial or Parallel uP Inteface 20 of 230 DS3170 DS3/E3 Single-Chip Transceiver TCLKI TSER TX BERT RX BERT UA1 IEEE P1149.1 GEN JTAG Test Access Port TCLKO TDEN RSER ...
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... Transmit HDB3 Formatter Encoder Trail FEAC Trace HDLC Buffer DS3 / E3 B3ZS/ Receive HDB3 Framer Decoder Serial or Parallel uP Inteface 21 of 230 DS3170 DS3/E3 Single-Chip Transceiver 1 1 TCLKO/TGCLK TSOFO/TDEN TCLKI TSER TSOFI TX BERT RX BERT RSER RCLKO/RGCLK RSOFO/RDEN UA1 IEEE P1149.1 GEN JTAG Test ...
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... MOSI, and MISO) SPI TLEN TZSD & RZSD PORT.CR2 0 1 TAIS TUA1 B3ZS/ HDB3 Encoder B3ZS/ HDB3 Decoder Serial or Parallel uP Inteface 22 of 230 DS3170 DS3/E3 Single-Chip Transceiver BERT RX BERT UA1 IEEE P1149.1 GEN JTAG Test Access Port TCLKO TDEN TCLKI TSER RSER RCLKO ...
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... X 1 TAIS TUA1 DS3 / E3 Transmit Formatter Trail FEAC Trace HDLC Buffer DS3 / E3 Receive Framer Serial or Parallel uP Inteface 23 of 230 DS3170 DS3/E3 Single-Chip Transceiver TCLKO/TGCLK TSOFO/TDEN TCLKI TSER TSOFI TX BERT RX BERT RSER RCLKO/RGCLK RSOFO/RDEN UA1 IEEE P1149.1 GEN JTAG Test Access Port ...
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... Clock Rate Adapter Serial Interface Mode: (SCLK, MOSI, and MISO) SPI TLEN TZSD & RZSD PORT.CR2 X 1 TAIS TUA1 Serial or Parallel uP Inteface 24 of 230 DS3170 DS3/E3 Single-Chip Transceiver TCLKO TDEN TCLKI TSER TX BERT RX BERT RSER RCLKO RDEN UA1 IEEE P1149.1 GEN ...
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... Note: In JTAG mode, all digital pins are bidirectional to increase the effectiveness of board level ATPG patterns for isolation of interconnect failures. 8.1 Short Pin Descriptions Table 8-1. DS3170 Short Pin Descriptions Ipu (input with pullup), Oz (output tri-stateable), Oa (Analog output), Ia (analog input), IO (Bidirectional in/out) NAME ...
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... POWER C1, K1, V K6, G10, SS A10, A2 B1, D1, V K4, K10, DD D10, A7 AVDDR C5 AVDDT F4 DS3170 DS3/E3 Single-Chip Transceiver TYPE IO Data [8] IO Data [7]/SPI Interface Clock Polarity IO Data [6]/SPI Interface Clock Phase IO Data [5:3]/SPI Bit Order Swap IO Data [4] IO Data [3] IO Data [2]/SPI Serial Interface Clock < 10 MHz ...
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... Analog Ground for Jitter Attenuator PWR Analog Ground for CLAD N/A Unused N/A Unused PIN DESCRIPTION Line IO TLEN). This clock is typically used as the clock reference for the TDAT (PORT.CR2. (PORT.CR2. TLEN), the un-encoded transmit signal 230 DS3170 DS3/E3 Single-Chip Transceiver FUNCTION TLEN), a high on this pin ...
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... RSOFO / RDEN, TSOFI, TSER, TSOFO / TDEN, TPOS / TDAT and TNEG signals. This input is ignored when the LIU is enabled. This input signal can be inverted. DS3: 44.736 MHz +20 ppm o E3: 34.368 MHz +20 ppm o DS3170 DS3/E3 Single-Chip Transceiver PIN DESCRIPTION (PORT.CR2. TLEN), a high on this pin 28 of 230 (Figure 2-1). This (Figure 2-1) ...
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... TOH pin. The TOHSOF signal marks the start of the framing bit sequence. This signal is sampled at the same time as the TOHCLK signal transitions high to low. This signal can be inverted. DS3170 DS3/E3 Single-Chip Transceiver PIN DESCRIPTION DS3/E3 Overhead Interface 29 of 230 ...
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... TNEG signals. This clock is not used when the part is in loop time mode or the CLAD clocks are used as the transmit clock source. (PORT.CR3.CLADC) This input signal can be inverted. DS3: 44.736 MHz +20 ppm o E3: 34.368 MHz +20 ppm o PIN DESCRIPTION DS3/E3 Serial Data Overhead Interface 30 of 230 DS3170 DS3/E3 Single-Chip Transceiver ...
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... TGCLK: When TGCLK is selected by PORT.CR3.TCLKS, this gated output clock is enabled. This gapped clock is the same clock as the internal framer transmit clock and is gated by TDEN. This clock is typically used for the reference clock for the TSER signal. This signal can be inverted. DS3170 DS3/E3 Single-Chip Transceiver PIN DESCRIPTION 31 of 230 ...
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... RLCLK clock input pin. This signal can be inverted. RDEN: When the port framer is configured for the DS3 or E3 framed modes and the RDEN pin function is enabled, this signal is used to indicate the DS3/E3 payload bit DS3170 DS3/E3 Single-Chip Transceiver PIN DESCRIPTION 32 of 230 ...
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... PIN DESCRIPTION Microprocessor Interface 1 = Output register bits 15:8 on D[7:0], D[15:8] not driven 0 = Output register bits 7:0 on D[7:0], D[15:8] not driven 1 = Output register bits 15:8 on D[7:0], 7:0 on D[15: Output register bits 7:0 on D[7:0], 15:8 on D[15: 230 DS3170 DS3/E3 Single-Chip Transceiver 8.3.4.1 8.3.4.1 for ...
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... GPIO7 IO General Purpose IO 7 PIN DESCRIPTION RD is low during a register read low during either a register read or a write low during a register write. R/W is high during a register read cycle, and low during a register write cycle. Misc I 230 DS3170 DS3/E3 Single-Chip Transceiver ...
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... AVDDT Analog 3.3V for transmit LIU PWR Powers transmit LIU AVDDJ Analog 3.3V for jitter attenuator PWR Powers jitter attenuator AVDDC Analog 3.3V for CLAD PWR Powers clock rate adapter DS3170 DS3/E3 Single-Chip Transceiver PIN DESCRIPTION JTAG CLAD POWER 35 of 230 ...
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... PIN NAME TYPE AVSSR PWR Analog Ground for receive LIU AVSST PWR Analog Ground for transmit LIU AVSSJ PWR Analog Ground for jitter attenuator AVSSC PWR Analog Ground for CLAD DS3170 DS3/E3 Single-Chip Transceiver PIN DESCRIPTION 36 of 230 ...
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... Figure 8-2 show the relationship between the analog and the digital outputs. Figure 8-1. Tx Line IO B3ZS Functional Timing Diagram TLCLK (TX DATA) TPOS TNEG TXP BIAS V TXN (TX LINE) - DS3170 DS3/E3 Single-Chip Transceiver B3ZS CODEWORD 37 of 230 Figure 2-1 for a diagram of the ...
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... Figure 8-3 and Figure 8-4 show the relationship between the analog and the digital outputs. Figure 8-3. Rx Line IO B3ZS Functional Timing Diagram RLCLK (RX DATA) RPOS RNEG RXP BIAS V RXN (RX LINE) - DS3170 DS3/E3 Single-Chip Transceiver HDB3 CODEWORD ...
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... The RDAT and RLCV signals are sampled at the rising edge of the reference clock signal if the clock pin is not inverted, otherwise they are sampled at the negative edge. The RLCLK clock pin is the clock reference used for the RDAT and RLCV signals. The RDAT and RLCV pins can be inverted. Please refer to DS3170 DS3/E3 Single-Chip Transceiver B V ...
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... FAS FAS FAS FAS FAS FAS FAS FAS FA1 FA1 FA1 FA1 FA1 FA1 FA2 FA2 230 DS3170 DS3/E3 Single-Chip Transceiver FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS FAS FA2 FA2 FA2 FA2 FA2 ...
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... FAS FAS FAS FAS FAS FAS FA2 FA1 FA1 FA1 FA1 FA1 FA1 FA2 FA2 230 DS3170 DS3/E3 Single-Chip Transceiver C21 C22 F23 C23 F24 F22 P1 F31 C31 FAS FAS FAS FAS FAS FAS FAS FA2 FA2 FA2 FA2 E M FA2 ...
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... DS3 or E3 overhead bits. The RSOFO signal marks the first overhead bit of the DS3 or E3 frame. Figure 8-16 to Figure 8-18 show the relationship between the receive serial interface pins. TSER DATA IS OVERWRITTEN WITH TSER DATA IS OVERWRITTEN WITH 230 DS3170 DS3/E3 Single-Chip Transceiver ...
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... When CPHA = 1, CS may remain asserted for more than one access without being toggled high and then low again between accesses. If the BURST bit is set, the address should increment and no additional control bytes are FAS 1111010000 FA1 11110110 230 DS3170 DS3/E3 Single-Chip Transceiver FA2 00101000 ...
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... SPI_CPHA. They indicate the clock edge that samples the data and the level of the clock during no-transfer events (high or low). Since the SPI port of the DS3170 acts as a slave device, the master device provides the clock. The user must configure the SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master device is providing ...
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... LSB of the address bus (A[0]). The selection of databus size is determined by the WIDTH input signal. See also Section 10.1. LSB MSB LSB MSB LSB MSB LSB MSB 45 of 230 DS3170 DS3/E3 Single-Chip Transceiver LSB MSB LSB MSB LSB MSB MSB LSB D2 D1 ...
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... Figure 8-27. 16-Bit Mode Write A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 Figure 8-28. 16-Bit Mode Read A[0]/BSWAP 0x2B0 A[10:1] D[15:0] 0x1234 RDY Z Note: Address 0x2B0 = 0x1234 DS3170 DS3/E3 Single-Chip Transceiver 230 ...
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... When the A[0]/BSWAP pin is set to 0, byte swapping is disabled, and when one, byte swapping is enabled. This pin should be static and not change while operating. Note: Address bit A[0] is not used in 16-bit mode. See also Section 10.1.3. DS3170 DS3/E3 Single-Chip Transceiver 0x2B0 0x12 ...
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... To use the Clear on Write method, the user must write the register with ones in the bit locations that he desires to clear. Figure 8-34 shows a read, a write, and then a subsequent read revealing the results of clearing of the bits, which he wrote a ‘1.’ See also Section 10.1.6. DS3170 DS3/E3 Single-Chip Transceiver 0x2B2 0x5678 Z Z ...
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... Ready Signal to describe the difference in access times to write or read to or from various memory locations on the DS3170 device. Some registers will have a faster access time than others and if needed, the user can implement the RDY signal to maximize efficiency of read and write accesses ...
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... D[15:0] 0x1234 RDY Z Figure 8-36. RDY Signal Functional Timing Read A[0]/BSWAP 0x1C0 A[10:1] D[15:0] 0xFFFF RDY Z Figure 16-8 and Figure See also 8.3.5 JTAG Functional Timing See Section 13.5. 0x3A4 0x0078 Z Z 0x3A4 0xFFFF Z Z 16- 230 DS3170 DS3/E3 Single-Chip Transceiver Z Z ...
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... PORT.CR2.LM[2:0] = 011 (LIU on side) or another setting. See PORT.CR2.FM[2:0] set to correct mode. See STEP 8: Disable Payload AIS (downstream AIS) and Line AIS PORT.CR1.PAIS[2:0] = 111 PORT.CR1.LAIS[1: STEP 9: Enable the port (for non-LIU modes) PORT.CR2.TLEN = 1 DS3170 DS3/E3 Single-Chip Transceiver GL.CR2. Table 10-26 Table 10-25 230 ...
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... One other potential problem is the Line Encoding/Decoding. The device needs to be configured in the same mode as the far end piece of equipment. If the far end piece of equipment is transmitting and receiving HDB3/B3ZS encoded data, the DS3170 also must be configured to do the same. This is controlled by the LINE.TCR.TZSD and the LINE.RCR.RZSD bits. ...
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... When LSBCRE=1, the latched register bits that are set will be cleared when the register is read. and Figure 8-29 for functional timing diagrams. Figure 8-35 for functional timing diagrams 230 DS3170 DS3/E3 Single-Chip Transceiver 8.3.4.1 for functional timing diagrams. for ...
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... If the data path reset is set during or after the mode change, the latched status bits will be automatically cleared. If the data path reset is not used to clear the latched status bits, then the registers must be cleared by reading or writing to them based on the register clear method selected. DS3170 DS3/E3 Single-Chip Transceiver Figure 8- 230 and Figure 8-34 ...
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... INTERRUPT ENABLE REGISTER Value Written Note 0x0002 Unmask OOF interrupt 0x0010 Unmask Port interrupts Value Read Note 0x0002 DS3 Out of Frame 0x0001 Framer Block Interrupt Active 0x0010 Port Interrupt Active 55 of 230 DS3170 DS3/E3 Single-Chip Transceiver PORT INTERRUPTS INT GLOBAL INTERRUPTS ...
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... In this mode, the RLCLK pin source the clock for the receive logic and the TCLKI pin sources the clock for the transmit logic. 10.2.1.2.4 LIU Disabled - CLAD Timing Enabled – this mode, the RLCLK pin source the clock for the receive logic and one of the CLAD clocks sources the clock for the transmit logic. DS3170 DS3/E3 Single-Chip Transceiver 56 of 230 ...
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... RLCLK or TCLKI or RXLIU CLAD RLCLK or TCLKI or RXLIU CLAD RLCLK or Same as RX RXLIU TCLKI or Same as Tx CLAD TCLKI or Same as Tx CLAD 57 of 230 DS3170 DS3/E3 Single-Chip Transceiver Tx LINE CLOCK SOURCE Same as Rx Same as Tx Same as Rx Same as Rx Same as Tx RLCLK or RXLIUn ...
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... Figure 10-2 shows the source of the TCLKO signals. Figure 10-2. Internal Tx Clock PORT.CR3. CLADC CLAD 0 TCLKI 1 RCLKO Table 10-4 identifies the source of the output signal TCLKO based on certain variables and register bits. DS3170 DS3/E3 Single-Chip Transceiver LLB or CLADC LIUEN PLB (PORT.CR3 ...
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... DIAGNOSTIC LOOPBACK 0 0 RCLKO 1 1 LBM[2:0] LIUEN (PORT.CR4) XXX 1 XXX 0 DLB disabled 1 0 disabled DLB (1XX DLB (1XX 230 DS3170 DS3/E3 Single-Chip Transceiver SOURCE Rx LIU RLCLK Rx LIU RLCLK CLAD TCLKI CLADC SOURCE (PORT.CR3 LIU X RLCLK X Rx LIU X RLCLK 0 CLAD 1 TCLKI 1 TCLKI ...
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... 16-1, will not be valid. There are some combinations of TFTS=1 and other 60 of 230 DS3170 DS3/E3 Single-Chip Transceiver VALID TIMING TO THESE CLOCK PINS TLCLK, TCLKO, RCLKO RLCLK No valid timing to any input clock pin TLCLK, TCLKO, RCLKO TLCLK, RCLKO TLCLK TLCLK, TCLKO (default) ...
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... X No valid timing to any clock pin Table 16-1, will not be valid. There are some combinations of RFTS=1 and other 61 of 230 DS3170 DS3/E3 Single-Chip Transceiver VALID TIMING TO THESE CLOCK PINS TCLKO, TLCLK, RCLKO RLCLK No valid timing to any input clock pin TCLKO, TLCLK, RCLKO ...
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... DS3170 DS3/E3 Single-Chip Transceiver VALID TIMING TO THESE CLOCK PINS ...
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... INTERNAL SIGNAL SET D Q DELAY Q CLR CLOCK TREE TLTS INTERNAL SIGNAL SET D Q DELAY Q CLR CLOCK TREE RFTS 63 of 230 DS3170 DS3/E3 Single-Chip Transceiver TDEN SET D Q PIN INVERT Q 0 CLR 1 TCLKO PIN INVERT TPOS SET D Q PIN INVERT Q 0 CLR 1 ...
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... SET SET GL.CR1. RST PORT.CR1. RST Q Q CLR CLR SET SET GL.CR1. RSTDP Q Q CLR CLR PORT.CR1. RSTDP SET CLR PORT.CR1 230 DS3170 DS3/E3 Single-Chip Transceiver Global Reset Port Reset Global Data Path Reset Port Data Path Reset Port Power Down ...
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... FEBE is enabled. Transmit clock comes from the REFCLK pin. The pin inversion on all pins is disabled. Individual blocks are reset and powered down when not used determined by the settings in the line mode bits PORT.CR2.LM[2:0] and framer mode bits PORT.CR2.FM[2:0]. INTERNAL SIGNALS 230 DS3170 DS3/E3 Single-Chip Transceiver ...
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... The 8KREF signal is only as accurate as the clock source chosen to generate it. Table 10-12 lists the selectable sources for global 8 kHz reference. DS3170 DS3/E3 Single-Chip Transceiver GL.CR2. G8KRS[2:0] bits 230 ...
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... The low to high edge on this signal will set the GL.SRL.ONESL latched one second detect bit which can generate an interrupt when the GL.SRIE.ONESIE interrupt enable bit is set. The low to high edge can also be used to generate performance monitor updates when GL.CR1.GPM[1:0]=1X. DS3170 DS3/E3 Single-Chip Transceiver SOURCE SOURCE ...
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... valid when a GPIO pin is not selected for a global signal Table 10-16 lists the various port alarm monitors that can be output on the GPIO pins. The GPIO(A/B)[3:0] bits are located in the PORT.CR4 Register. CONTROL BIT GL.CR2.G8KOS GL.CR2.G8KIS GL.CR1.MEIMS GL.CR1.GPM[1: 230 DS3170 DS3/E3 Single-Chip Transceiver ...
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... The latched PMS signal can be used to generate an interrupt for reading the count registers. If the port is not configured for global PMU signals, the PMS signal from that port should be blocked from affecting the global PMS status 230 DS3170 DS3/E3 Single-Chip Transceiver ...
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... When bit MEIMS=0, errors are inserted using other bits in the transmit error insertion register. When bit MEIMS=1, errors are inserted using a signal generated in the port or global control registers or using the external GPIO6 pin configured for TMEI operation. other port counters 0 PMU PMS PERF 1 COUNTER GTZ 70 of 230 DS3170 DS3/E3 Single-Chip Transceiver GL.SR.GPMS PORT.SR.PMS ...
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... LBM[2:0] ALB LLB 000 0 0 001 1 0 010 0 1 011 0 0 10X 0 0 110 0 1 111 0 0 BERT.TEICR.MEIMS BERT.TEICR error insertion bit 0 1 T3.TEIR error insertion bit PLB DLB 230 DS3170 DS3/E3 Single-Chip Transceiver 0 BERT ERROR INSERT 1 T3.TEIR.MEIMS 0 T3 ERROR INSERT ...
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... Figure 10-10. ALB Mux TXP TXN RXP RXN TAIS TUA1 DS3 / E3 Transmit Formatter Trail FEAC Trace HDLC Buffer DS3 / E3 Receive Framer UA1 IEEE P1149.1 GEN JTAG Test Access Port TX LIU RX LIU 72 of 230 DS3170 DS3/E3 Single-Chip Transceiver TX BERT RX BERT Microprocessor Interface ...
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... DS3 AIS signal is being generated. A sequence of events can be executed which will enable the initiation and termination of DS3 AIS or unframed all ones at the top level without any errors introduced. 10-9. Table 73 of 230 DS3170 DS3/E3 Single-Chip Transceiver Figure 10-9. 10-18). The AIS signal is an unframed all and P ) ...
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... FRAMER 0 0 B3ZS/ 1 HDB3 1 TAIS TAIS DS3/ UA1 DS3/ AIS UA1 AIS TSOFO DS3/UA1 AIS detector 1 B3ZS/ 0 HDB3 DLB UA1 AIS 74 of 230 DS3170 DS3/E3 Single-Chip Transceiver TRANSMIT 0 PAYLOAD 1 PLB SYSTEM/ TRUNK SIDE 0 0 RECEIVE 1 PAYLOAD 1 DAIS DAIS UA1 AIS ...
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... Automatic AIS when DLB is enabled (PORT.CR4.LBM = 1XX) Automatic AIS when DLB is enabled Send UA1 Send AIS Send AIS Disable AIS CODE UA1 UA1 UA1 UA1 UA1 UA1 UA1 none 75 of 230 DS3170 DS3/E3 Single-Chip Transceiver AIS CODE DS3AIS UA1 UA1 DS3AIS UA1 none ...
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... PORT.CR3.RPFPE, PORT.CR3.RSOFOS and PORT.CR3.RCLKS. Table 10-23 to Table 10-24 describe the function selected by the FM bits and other pin mode bits for the multiplexed pins. PIN FUNCTION TDEN TSOFO High PIN GAP SOURCE FUNCTION TGCLK TDEN TCLKO none TCLKO none 76 of 230 DS3170 DS3/E3 Single-Chip Transceiver ...
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... High PIN GAP SOURCE FUNCTION RGCLK RDEN RCLKO none RCLKO none LINE CODE B3ZS/AMI/UNI B3ZS/AMI/UNI HDB3/AMI/UNI HDB3/AMI/UNI B3ZS/AMI/UNI --- HDB3/AMI/UNI --- 77 of 230 DS3170 DS3/E3 Single-Chip Transceiver FIGURE Figure 7-1 Figure 7-1 Figure 7-1 Figure 7-1 Figure 7-2 Figure 7-2 Table 10-26 for ...
Page 78
... LINE.TCR.TZSD & LM[2:0] LINE.RCR.RZSD (PORT.CR2) 0 000 0 001 0 010 0 011 1 000 1 001 1 010 1 011 X 1XX Line Code LIU B3ZS/HDB3 OFF B3ZS/HDB3 ON B3ZS/HDB3 ON B3ZS/HDB3 ON AMI OFF AMI ON AMI ON AMI ON UNI OFF 78 of 230 DS3170 DS3/E3 Single-Chip Transceiver JA OFF OFF TX RX OFF OFF TX RX OFF ...
Page 79
... The Transmit DS3/E3 Formatter receives a DS3/E3 payload on TSER, generates a DS3/E3 frame, optionally inserts DS3/E3 overhead, and transmits the DS3/E3 signal. Refer to Figure 10-12 for the location of the DS3/E3 Framer/Formatter blocks in the DS3170. Figure 10-12. Framer Detailed Block Diagram B3ZS/ DS3/E3 HDB3 ...
Page 80
... The DS3 framer has a Maximum Average Reframe Time (MART) of approximately 1.0 ms and M , which have a value of zero, one, and zero respectively. The DS3 230 DS3170 DS3/E3 Single-Chip Transceiver , F X1 Figure 10-13. Once the subframe , ...
Page 81
... OOF or OOMF condition is present. The multiframe framer waits until a subframe boundary has been identified. Then, each bit position is checked for the multiframe 680 Bits Sync Load 81 of 230 DS3170 DS3/E3 Single-Chip Transceiver Sub Frames ...
Page 82
... A Severely Errored Frame (SEF) condition is declared when three or more out of the last sixteen consecutive F-bits have been errored, or when a manual resynchronization is requested. An SEF condition is terminated when an OOF condition is absent. Figure 10-15 for the multiframe framer state diagram. Sync Timeout Load 82 of 230 DS3170 DS3/E3 Single-Chip Transceiver Figure 10-15 for the multiframe ...
Page 83
... X ) set to zero. An RDI condition is terminated when 1 2 and the next DS3 frame. If the calculated parity does not single C-bit parity error is declared 230 DS3170 DS3/E3 Single-Chip Transceiver and X ) are set to one and P ). The X-bits (X and and the next DS3 frame. ...
Page 84
... Table 10-27 shows the function of each overhead bit in the DS3 Frame bit is set to one in thirty-one consecutive multiframes. The AIC is set to zero (M23 Figure 10-13 680 Bits 84 of 230 DS3170 DS3/E3 Single-Chip Transceiver , C , and value of 111 bit. The AIC Sub Frames ...
Page 85
... and C are all overwritten with a one 230 DS3170 DS3/E3 Single-Chip Transceiver are the subframe XY is reserved for future network use, and has and C are unused, and have a value and and C ...
Page 86
... C , and C are overwritten with the calculated payload parity from the previous ≠ 3) are overwritten with 000. AIS will overwrite a transmit Idle signal 230 DS3170 DS3/E3 Single-Chip Transceiver , error. An SEF error and OOMF error is a single multiframe X4 and single DS3 frame ...
Page 87
... and F ) are overwritten with the values one, zero, zero, and one (1001 230 DS3170 DS3/E3 Single-Chip Transceiver are the subframe alignment bits that XY are the Far-End Block Error (FEBE) bits 43 are unused, and have a value of one and C bits are sent to the receive HDLC ...
Page 88
... DS3 frame 230 DS3170 DS3/E3 Single-Chip Transceiver , error. An SEF error and F ) ...
Page 89
... and C are the stuff control bits for tributary # Figure 10-16. FAS is the Frame Alignment Signal the Alarm indication 1524 Bit Payload 384 bits 89 of 230 DS3170 DS3/E3 Single-Chip Transceiver , are the subframe alignment bits that Rows , and the ...
Page 90
... OOF condition is absent, and it is reset when an OOF condition is absent for T continuous ms programmable ( 3). An LOF condition is terminated when an OOF condition is absent for T continuous ms. Figure 10-16. FAS is the Frame Alignment Signal the Alarm indication 90 of 230 DS3170 DS3/E3 Single-Chip Transceiver ...
Page 91
... Downstream AIS is removed when all OOF, LOS, and AIS conditions are terminated and manual downstream AIS insertion is disabled. RPDT will be forced to all ones during downstream AIS. 10.6.8 G.832 E3 Framer/Formatter 10.6.8.1 Transmit G.832 E3 Frame Processor The G.832 E3 frame format is shown in Figure 10-17 230 DS3170 DS3/E3 Single-Chip Transceiver ...
Page 92
... Table 10-29. G.832 E3 Frame Overhead Bit Definitions BYTE DEFINITION FA1, FA2 Frame Alignment bytes EM Error Monitoring byte TR Trail Trace byte MA Maintenance and Adaption byte NR Network Operator byte GC General Purpose Communication Channel byte 530 Byte Payload 59 Columns LSB 230 DS3170 DS3/E3 Single-Chip Transceiver 9 Rows ...
Page 93
... D7h are inserted in the FA1 and FA2 bytes respectively). Framing error(s) can be inserted one error at a time, or four consecutive frames. The framing error insertion mode (single or four) is programmable. DS3170 DS3/E3 Single-Chip Transceiver Figure 93 of 230 ...
Page 94
... OOF condition is absent, and it is reset when an OOF condition is absent for T continuous ms programmable ( 3). An LOF condition is terminated when an OOF condition is absent for T continuous ms. DS3170 DS3/E3 Single-Chip Transceiver Figure 10-17. FA1 and FA2 are the Frame Alignment bytes the 94 of 230 ...
Page 95
... The payload type (third, fourth, and fifth bits of the MA byte) is integrated and stored in a register with change and unstable indications. The integrated received payload type is also compared against an expected payload type. If the received and expected payload types do not match (see DS3170 DS3/E3 Single-Chip Transceiver Table 10-30), a mismatch indication is set. ...
Page 96
... HDLC Overhead Controller 10.7.1 General Description The DS3170 device contains a built-in HDLC controller with 256 byte FIFOs for insertion/extraction of DS3 PMDL, G.751 Sn bit and G.832 NR/GC bytes. The HDLC Overhead Controller demaps HDLC overhead packets from the DS3/E3 data stream in the receive direction and maps HDLC packets into the DS3/E3 data stream in the transmit direction ...
Page 97
... However, when a byte is stored in a register, the MSB is stored in the lowest numbered bit (0), and the LSB is stored in the highest numbered bit (7). This is to differentiate between a byte in a register and the corresponding byte in a signal. See Figure 10-19 for the location of HDLC controllers within the DS3170 device. Figure 10-19. HDLC Controller Block Diagram B3ZS/ DS3/E3 HDB3 ...
Page 98
... The inter-frame fill can be flags (01111110) or all '1's. When inter-frame fill is all ‘1’s, the number of '1's between the end flag and the start flag may not be an integer number of bytes. When inter-frame fill is flags, the DS3170 DS3/E3 Single-Chip Transceiver 16 ...
Page 99
... FIFO is empty, the read is ignored, and an invalid data indication given. 10.8 Trail Trace Controller 10.8.1 General Description The DS3170 has a dedicated Trail Trace Buffer for E3-G.832 link management The Trail Trace Controller performs extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register. ...
Page 100
... It removes the trace identifier data from the data storage, performs trace ID processing, and outputs the trace ID data stream. Refer to location of the Trail Trace Controller with the DS3170 device. Figure 10-20. Trail Trace Controller Block Diagram ...
Page 101
... MAS are verified as being zero. The MAS check is performed one byte at a time. Multiframe alignment is programmable (on or off). When multiframe alignment is disabled, the incoming bytes are sequentially stored starting with a random byte. DS3170 DS3/E3 Single-Chip Transceiver (Figure 10-21). The MAS bits are each ...
Page 102
... The receive direction performs FEAC processing, and stores the codewords in the FIFO using line timing. It removes the codewords from the FIFO and outputs them to the microprocessor via the register interface. Bit 4 Bit 5 Bit 6 DT[4] DT[5] DT[6] Figure 10-21) of each trail trace identifier byte (The 102 of 230 DS3170 DS3/E3 Single-Chip Transceiver Bit 7 Bit 8 LSB DT[7] DT[8] ...
Page 103
... Then the code from TFCB[5:0] is inserted into a codeword, and sent ten consecutive times. Once both codewords DS3 / E3 Transmit Formatter Trail FEAC Trace HDLC Buffer DS3 / E3 Receive Framer UA1 IEEE P1149.1 GEN JTAG Test Access Port 103 of 230 DS3170 DS3/E3 Single-Chip Transceiver Figure 10-22 for the location of the TX BERT RX BERT Microprocessor Interface ...
Page 104
... If the port line interface is configured for a Unipolar mode, the BPV detector will count pulses on the RLCV pin. See Figure 10-24 for the locations of the Line Encoder/ Decorder block in the DS3170 device. DS3170 DS3/E3 Single-Chip Transceiver Receive/Transmit Order ...
Page 105
... AMI rules. The second bipolar one is generated by transmitting the same values on TPOS and TNEG DS3 / E3 Transmit Formatter Trail FEAC Trace HDLC Buffer DS3 / E3 Receive Framer UA1 IEEE P1149.1 GEN JTAG Test Access Port 105 of 230 DS3170 DS3/E3 Single-Chip Transceiver TX BERT RX BERT Microprocessor Interface ...
Page 106
... Figure 10-26. Zero suppression decoding is also programmable (on or off). Note: Immediately after a reset or a LOS condition, the first B3ZS/HDB3 signature to be detected will not depend upon the polarity of any BPV contained within the signature. DS3170 DS3/E3 Single-Chip Transceiver 106 of 230 Figure ...
Page 107
... Immediately after a reset (or datapath reset LOS condition, a BPV will not be declared when the first valid one (RPOS high and RNEG low, or RPOS low and RNEG high) is received. Bipolar to unipolar conversion converts the AMI bipolar data into a unipolar signal by OR’ing together the RXP and RXN signals. DS3170 DS3/E3 Single-Chip Transceiver V B3ZS SIGNATURE WHEN LINE ...
Page 108
... The following tables show how to configure the on-board BERT to send and receive common patterns where n and y can take on values from and to Figure 10-27 for the location of the BERT Block within the DS3170 DS3 / E3 Transmit Formatter Trail FEAC Trace ...
Page 109
... BERT.SR Register which contains the Bit Error Count (BEC) bit and the 109 of 230 DS3170 DS3/E3 Single-Chip Transceiver BERT. BERT. BERT. PCR SPR2 SPR1 0x0408 0xFFFF 0xFFFF 0x080A 0xFFFF 0xFFFF 0x0D0E 0xFFFF 0xFFFF 0x1013 0xFFFF 0xFFFF 0x0253 0xFFFF 0xFFFF 0x1116 0xFFFF 0xFFFF BERT ...
Page 110
... If at least six incoming bits in the current 64-bit window do not match the receive PRBS pattern generator, automatic pattern resynchronization is initiated. Automatic pattern resynchronization can be disabled. Refer to Figure 10-29 for the repetitive pattern synchronization state diagram. Sync Load 110 of 230 DS3170 DS3/E3 Single-Chip Transceiver ...
Page 111
... The method of single error insertion is programmable (register or input). If pattern inversion is enabled, the data stream is inverted before the overhead/stuff bits are inserted. Pattern inversion is programmable (on or off). DS3170 DS3/E3 Single-Chip Transceiver Match ...
Page 112
... The line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3 or E3 lines. The LIU has independent receive and transmit paths and a built-in jitter attenuator. See location within the DS3170 device of the LIU. Figure 10-30. LIU Functional Diagram ...
Page 113
... DS3/E3 REFCLK Clock Rate Adapter Gain Clock & + Data Recovery ALOS squelch 113 of 230 DS3170 DS3/E3 Single-Chip Transceiver Table 5-1. Figure 2-1 TO B3ZS/HDB3 DECODER FROM B3ZS/HDB3 ENCODER Table 16-7 through Table 16-9 shows the and ...
Page 114
... Table 5-1. Table 10-33 VALUE 1:2ct ±2% 0.250MHz to 500MHz (typ) 19µH (min) 0.12µH (max) 10pF (max) 1500V (min) RMS 114 of 230 DS3170 DS3/E3 Single-Chip Transceiver Figure 2-1 shows the arrangement of the specifies the required characteristics of ...
Page 115
... SCHEMATIC 6 SMT 0°C to +70°C LS-1/C 6 Thru-Hole 0°C to +70°C LC-1/C 6 SMT 0°C to +70°C SMD/B 6 DIP 0°C to +70°C DIP/B 115 of 230 DS3170 DS3/E3 Single-Chip Transceiver OCL L L BANDWIDTH PRIMARY (µH) 75Ω (MHz) (µH) (min) (max) 19 0.06 0.250 to 500 19 0.06 ...
Page 116
... Figure 10-32. Receiver Jitter Tolerance 15 DS3 GR-499 Cat II 10 DS3 GR-499 Cat I 1.0 0.1 10 STS-1 GR253 10 5 1.5 E3 G.823 30 300 669 2.3k 100 1k FREQUENCY (Hz) 116 of 230 DS3170 DS3/E3 Single-Chip Transceiver DS3170 JITTER TOLERANCE 0.3 0.15 0.1 22.3k 60k 300k 800k 10k 100k 1M ...
Page 117
... The RDY signal will go active if the user writes or reads reserved registers or unused registers within design blocks. Table 11-1. Register Address Map Description Address offset 000 - 01F Global registers 020 – 03F Unused 040 - 05F Port control registers 060 – 07F BERT 080 – 08B Unused DS3170 DS3/E3 Single-Chip Transceiver 117 of 230 ...
Page 118
... Trail Trace Receive 100 – 117 Unused 118 – 11F DS3/E3 Framer Transmit 120 – 13F DS3/E3 Framer Receive 140 – 17F Unused 180 – 19F Test Registers 1A0 – 1FF Unused DS3170 DS3/E3 Single-Chip Transceiver 118 of 230 ...
Page 119
... GPIO8 GPIO7 GPIO6 GPIO5 -- -- -- -- -- -- -- -- -- Bit 6 Bit 5 Bit 4 Bit 15 Bit 14 Bit 13 Bit 12 119 of 230 DS3170 DS3/E3 Single-Chip Transceiver Bit 3 Bit 2 Bit 1 Bit 11 Bit 10 Bit 9 ID4 ID3 ID2 ID1 ID11 ID10 ID9 PMU LSBCRE RSTDP -- -- -- -- -- CLAD2 CLAD1 CLAD0 -- G8KRS1 G8KRS0 G8K0S ...
Page 120
... DS3170 DS3/E3 Single-Chip Transceiver Bit 3 Bit 2 Bit 1 Bit 11 Bit 10 Bit 9 PMU PD RSTDP LAIS1 LAIS0 BENA FM0 RES RES RES LM2 LM1 CLADC RFTS TFTS RES TCLKS TSOFOS ...
Page 121
... TFD7 TFD6 TFD5 TFD4 -- -- -- -- -- TFFL5 TFFL4 -- -- TFOL TFUL -- -- -- -- -- TFOIE TFUIE -- -- -- 121 of 230 DS3170 DS3/E3 Single-Chip Transceiver Bit 3 Bit 2 Bit 1 Bit 11 Bit 10 Bit 9 BEC3 BEC2 BEC1 BEC11 BEC10 BEC9 BEC19 BEC18 BEC17 -- -- -- -- BC3 BC2 BC1 BC11 BC10 BC9 BC19 BC18 BC17 ...
Page 122
... RFFI -- RFF5 RFF4 -- -- -- -- -- -- -- -- -- 122 of 230 DS3170 DS3/E3 Single-Chip Transceiver Bit 3 Bit 2 Bit 1 Bit 11 Bit 10 Bit RBRE RDIE RFPD RDAL3 RDAL2 RDAL1 -- -- -- -- -- -- -- -- -- -- RFF RFE -- -- -- -- RPSL RFFL -- -- -- -- ...
Page 123
... Reserved COVHD MAOD MDAISI -- -- -- -- -- -- OOMF SEF -- LOF Reserved Reserved -- Reserved -- -- -- -- -- -- OOMFL SEFL COFAL LOFL Reserved Reserved Reserved Reserved 123 of 230 DS3170 DS3/E3 Single-Chip Transceiver Bit 3 Bit 2 Bit 1 Bit 11 Bit 10 Bit 9 TMAD TIDLE TDIE -- -- -- -- TTIA3 TTIA2 TTIA1 -- -- -- -- TTD3 TTD2 TTD1 -- -- -- -- -- ...
Page 124
... Reserved Reserved Reserved Reserved Reserved Reserved Reserved RUA1IE -- -- -- -- -- -- -- -- -- -- -- -- FE7 FE6 FE5 FE4 FE15 FE14 FE13 FE12 124 of 230 DS3170 DS3/E3 Single-Chip Transceiver Bit 3 Bit 2 Bit 1 Bit 11 Bit 10 Bit 9 -- CPECL FBECL PECL -- CPEL FBEL PEL RAIIE AISIE OOFIE AICIE IDLEIE -- CPECIE FBECIE ...
Page 125
... FE13 FE12 PE7 PE6 PE5 PE4 PE15 PE14 PE13 PE12 FBE7 FBE6 FBE5 FBE4 FBE 15 FBE 14 FBE 13 FBE -- -- -- -- -- -- -- -- -- -- -- -- 125 of 230 DS3170 DS3/E3 Single-Chip Transceiver Bit 3 Bit 2 Bit 1 Bit 11 Bit 10 Bit Bit 3 Bit 2 Bit 1 Bit 11 Bit 10 Bit 9 TRDI ARDID TFGD TGCC TNRC1 ...
Page 126
... Bits Device CODE ID Bits (ID11 to ID0). These bits of the device code ID register has same information as the lower 12 bits of JTAG CODE ID portion of the JTAG ID register. JTAG ID[23:12]. GL.IDR Global ID Register 000h 13 12 ID13 ID12 ID11 5 4 ID5 ID4 126 of 230 DS3170 DS3/E3 Single-Chip Transceiver ID10 ID9 ID3 ID2 ID1 8 ID8 0 ...
Page 127
... RST bit), will be reset to their default state. This bit must be set high for a minimum of 100ns. See the Power-Down section 10. Normal operation 1 = Force all internal registers to their default values GL.CR1 Global Control Register 1 002h GPM1 GPM0 PMU 0 0 127 of 230 DS3170 DS3/E3 Single-Chip Transceiver LSBCRE RSTDP Reset and Power-Down RST 0 section 10 ...
Page 128
... MHz 011 19.44 MHz 100 77.76 MHz 101 Undefined 11X Undefined GL.CR2 Global Control Register 2 004h G8KRS1 CLAD2 0 0 SOURCE GL.GIOCR. GPIO2S[1:0] GL.GIOCR. GPIO4S[1:0] 128 of 230 DS3170 DS3/E3 Single-Chip Transceiver G8KRS0 G8K0S CLAD1 CLAD0 GL.CR2.8KRS[2:0] Table 10-11. 8 G8KIS Table ...
Page 129
... Port B status output selected by PORT.CR4:GPIOB[3:0] in port control registers 10 = Output logic Output logic 1 GL.GIOCR Global General Purpose IO Control Register 00Ah 13 12 GPIO7S1 GPIO7S0 GPIO6S1 GPIO3S1 GPIO3S0 GPIO2S1 0 0 GL.CR2 .G8KRIS=0. 129 of 230 DS3170 DS3/E3 Single-Chip Transceiver GPIO6S0 GPIO5S1 GPIO2S0 GPIO1S1 GPIO5S0 0 0 GPIO1S0 0 ...
Page 130
... GL.ISR.GSR status bit is set, the INT pin will be driven low interrupt disabled 1 = interrupt enabled GL.ISR Global Interrupt Status Register 010h PISR GL.ISRIE Global Interrupt Status Register Interrupt Enable 012h PISRIE 0 0 130 of 230 DS3170 DS3/E3 Single-Chip Transceiver RESERVED 0 0 ...
Page 131
... GL.SRIE.GPMSIE is enabled. GL.ISRIE.GSRIE bit are enabled. GL.SR Global Status Register 014h GL.SRL Global Status Register Latched 016h 8KREFL CLADL This bit will drive the interrupt pin low if the GL.SRIE.GPMSIE bit and the 131 of 230 DS3170 DS3/E3 Single-Chip Transceiver CLOL ONESL CLOLL ...
Page 132
... Bits General Purpose IO Status [8:1]] (GPIO[8:1] ) These bits reflect the input or output signal on the 8 general purpose IO pins. GL.SRIE Global Status Register Interrupt Enable 018h GL.GIORR Global General Purpose IO Read Register 01Ch GPIO6 GPIO5 GPIO4 132 of 230 DS3170 DS3/E3 Single-Chip Transceiver ONESIE CLOLIE GPIO3 GPIO2 ...
Page 133
... Port IO Invert Control Register 2 0 4Eh -- Unused 0 50h PORT.ISR Port Interrupt Status Register 0 PORT.SR 52h Port Status Register 0 54h PORT.SRL Port Status Register Latched 0 56h PORT.SRIE Port Status Register Interrupt Enable 0 58h -- Unused 0 5Ah -- Unused 0 5Ch -- Unused 0 5Eh -- Unused 0 DS3170 DS3/E3 Single-Chip Transceiver 133 of 230 ...
Page 134
... UA1 UA1 UA1 UA1 UA1 UA1 UA1 none DESCRIPTION Automatic AIS when DLB is enabled (PORT.CR4 .LBM = 1XX) Automatic AIS when DLB is enabled Send UA1 Send AIS Send AIS Disable 134 of 230 DS3170 DS3/E3 Single-Chip Transceiver LAIS0 BENA RSTDP AIS CODE DS3AIS ...
Page 135
... It has no effect when the LIU is disabled and powered down. Reset and Power-Down PORT.CR2 Port Control Register 2 042h 13 12 RESERVED RMON TLBO FM2 FM1 FM0 0 0 135 of 230 DS3170 DS3/E3 Single-Chip Transceiver Reset and Power-Down Reset and Power- section 10.3. This bit must LM2 LM1 RESERVED RESERVED ...
Page 136
... AMI OFF AMI ON AMI ON AMI ON UNI OFF LINE CODE B3ZS/AMI/UNI B3ZS/AMI/UNI HDB3/AMI/UNI HDB3/AMI/UNI B3ZS/AMI/UNI --- HDB3/AMI/UNI --- 136 of 230 DS3170 DS3/E3 Single-Chip Transceiver JA OFF OFF TX RX OFF OFF TX RX OFF FIGURE Figure 7-1 Figure 7-1 Figure 7-1 Figure 7-1 Figure 7-2 Figure 7-2 ...
Page 137
... Do not use CLAD clocks for the transmit clock – (if no loopback is enabled, TCLKI is the source) PORT.CR3 Port Control Register 3 044h 13 12 RCLKS RSOFOS RESERVED P8KREF LOOPT CLADC 0 0 SOURCE 137 of 230 DS3170 DS3/E3 Single-Chip Transceiver TCLKS TSOFOS RFTS TFTS Table 10-4 for more details. 8 ...
Page 138
... GPIOB1 GPIOB0 GPIOA3 0 0 PLB DLB Table 10-15. Table 10-16 138 of 230 DS3170 DS3/E3 Single-Chip Transceiver Table 10-8 Table 10-6 for more details LBM2 LBM1 GPIOA2 GPIOA1 Table 10-17 for the loopback GL.GIOCR See Table 10-16 for the alarm select below for the alarm select codes ...
Page 139
... Table 10-16. GPIO Port Alarm Monitor Select PORT.CR4 GPIO(A/B)[3:0] 0000 X 0001 X 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 X 1100 1101 X 1110 1111 139 of 230 DS3170 DS3/E3 Single-Chip Transceiver ...
Page 140
... Bit 1 : RCLKO / RGCLK Invert (RCLKOI). This bit inverts the RCLKO / RGCLK pin when set. PORT.INV1 Port IO Invert Control Register 1 04Ah TSOFOI RESERVED TSOFII TNEGI TDATI 0 0 PORT.INV2 Port IO Invert Control Register 2 04Ch 13 12 RESERVED RSOFOI RNEGI RPOSI 0 0 140 of 230 DS3170 DS3/E3 Single-Chip Transceiver TSERI TOHSI TLCKI TCKOI RSERI ROHSI RLCKI RCLKOI ...
Page 141
... Bit 2: Transmit Driver Monitor Status (TDM) This bits indicates the status of the transmit monitor circuit in the transmit LIU Transmit output not over loaded 1 = Transmit signal is overloaded PORT.ISR Port Interrupt Status Register 050h HSR BSR RESERVED PORT.SR Port Status Register 052h 141 of 230 DS3170 DS3/E3 Single-Chip Transceiver PSR RESERVED RESERVED TDM RLOL 8 LCSR 0 FMSR ...
Page 142
... Bit 2: Transmit Driver Monitor Latched Status Interrupt Enable (TDMIE) The interrupt pin will be driven when this bit is enabled and the PORT.SRL.TDML bit is set and the GL.ISRIE.PISRIE bit is enabled. PORT.SRL Port Status Register Latched 054h PORT.SRIE Port Status Register Interrupt Enable 056h 142 of 230 DS3170 DS3/E3 Single-Chip Transceiver TDML RLOLL TDMIE RLOLIE 0 ...
Page 143
... PORT.SRL.RLOLL bit is set and the bit in GL.ISRIE.PISRIE bit is enabled. Bit 0: Performance Monitoring Update Latched Status Interrupt Enable (PMSIE) The interrupt pin will be driven when this bit is enabled and the PORT.SRL.PMSL bit is set and the bit in GL.ISRIE.PISRIE bit is enabled. DS3170 DS3/E3 Single-Chip Transceiver 143 of 230 ...
Page 144
... BERT Receive Bit Error Count Register #1 BERT Receive Bit Error Count Register #2 BERT Receive Bit Count Register #1 BERT Receive Bit Count Register #2 Unused Unused BERT.CR BERT Control Register 060h RNPL RPIC MPR 0 0 144 of 230 DS3170 DS3/E3 Single-Chip Transceiver APRD TNPL TPIC ...
Page 145
... XOR of bit n and bit y. For a repetitive pattern the feedback is bit n. BERT.PCR BERT Pattern Configuration Register 062h PTF4 PTF3 PTS PLF4 PLF3 The output of the pattern generator will be forced to one if the next fourteen 145 of 230 DS3170 DS3/E3 Single-Chip Transceiver PTF2 PTF1 PLF2 PLF1 PTF0 0 ...
Page 146
... BERT.TEICR BERT Transmit Error Insertion Control Register 068h TEIR2 TEIR1 TEIR0 bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value th bit being inverted. Error insertion starts when this register is written to with 146 of 230 DS3170 DS3/E3 Single-Chip Transceiver BSP10 BSP9 BSP2 BSP1 BSP26 ...
Page 147
... This bit is cleared when the user updates the BERT counters via the PMU bit (BERT.CR). Bit 0: Out Of Synchronization (OOS) – When 0, the receive pattern generator is synchronized to the incoming pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern. BERT.SR BERT Status Register 06Ch PMS 147 of 230 DS3170 DS3/E3 Single-Chip Transceiver BEC OOS ...
Page 148
... Bit 0: Out Of Synchronization Interrupt Enable (OOSIE) – This bit enables an interrupt if the OOSL bit is set and the GL.ISRIE.PSRIE bit is set interrupt disabled 1 = interrupt enabled BERT.SRL BERT Status Register Latched 06Eh PMSL BERT.SRIE BERT Status Register Interrupt Enable 070h PMSIE 0 0 148 of 230 DS3170 DS3/E3 Single-Chip Transceiver BEL BECL BEIE BECIE OOSL ...
Page 149
... OOS condition exists. This register is updated via the PMU signal (see section 10.4.5) BERT.RBECR1 BERT Receive Bit Error Count Register #1 074h 13 12 BEC13 BEC12 BEC11 BEC5 BEC4 BEC3 0 0 BERT.RBECR2 BERT Receive Bit Error Count Register #2 076h BEC21 BEC20 BEC19 0 0 149 of 230 DS3170 DS3/E3 Single-Chip Transceiver BEC10 BEC9 BEC2 BEC1 BEC18 BEC17 ...
Page 150
... Receive Bit Count Register #1 078h 13 12 BC13 BC12 BC11 BC5 BC4 0 0 BERT.RBCR2 Receive Bit Count Register #2 07Ah 13 12 BC29 BC28 BC27 BC21 BC20 BC19 0 0 150 of 230 DS3170 DS3/E3 Single-Chip Transceiver BC10 BC9 BC3 BC2 BC1 BC26 BC25 BC18 BC17 0 0 ...
Page 151
... When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is one, changing the state of this bit may cause an error to be inserted. Register Description Line Transmit Control Register Unused LINE.TCR Line Transmit Control Register 08Ch TZSD EXZI 0 0 151 of 230 DS3170 DS3/E3 Single-Chip Transceiver BPVI TSEI ...
Page 152
... Line Receive Status Register Latched Line Receive Status Register Interrupt Enable Unused Line Receive Bipolar Violation Count Register Line Receive Excessive Zero Count Register LINE.RCR Line Receive Control Register (0.2.4.6)90h E3CVE 0 0 152 of 230 DS3170 DS3/E3 Single-Chip Transceiver REZSF RDZSF RZSD ...
Page 153
... Note: When zero suppression (B3ZS or HDB3) decoding is disabled, the LOS condition is cleared, and cannot be detected. LINE.RSR Line Receive Status Register (0.2.4.6)94h EXZC 10.10.4 LINE.RSRL Line Receive Status Register Latched (0.2.4.6)96h ZSCDL EXZL EXZCL 153 of 230 DS3170 DS3/E3 Single-Chip Transceiver BPVC BPVL BPVCL LOS 8 ...
Page 154
... This register is updated via the PMU signal (see section 10.4.5) LINE.RSRIE Line Receive Status Register Interrupt Enable (0.2.4.6)98h ZSCDIE EXZIE EXZCIE 0 0 LINE.RBPVCR Line Receive Bipolar Violation Count Register (0.2.4.6)9Ch 13 12 BPV13 BPV12 BPV11 BPV5 BPV4 BPV3 0 0 154 of 230 DS3170 DS3/E3 Single-Chip Transceiver BPVIE BPVCIE BPV10 BPV9 BPV2 BPV1 ...
Page 155
... This register is updated via the PMU signal (see section 10.4.5) LINE.REXZCR Line Receive Excessive Zero Count Register (0.2.4.6)9Eh 13 12 EXZ13 EXZ12 EXZ11 EXZ5 EXZ4 EXZ3 0 0 155 of 230 DS3170 DS3/E3 Single-Chip Transceiver EXZ10 EXZ9 EXZ2 EXZ1 EXZ8 0 ...
Page 156
... HDLC Transmit Status Register HDLC Transmit Status Register Latched HDLC Transmit Status Register Interrupt Enable Unused Unused Unused HDLC.TCR HDLC Transmit Control Register 0A0h TDAL4 TDAL3 TFEI TIFV TBRE 0 0 156 of 230 DS3170 DS3/E3 Single-Chip Transceiver TDAL2 TDAL1 TDIE TFPD TDAL0 0 0 TFRST 0 ...
Page 157
... Transmit FIFO has the same or more storage space available than the Transmit FIFO HDLC data storage available level. HDLC.TFDR HDLC Transmit FIFO Data Register 0A2h 13 12 TFD5 TFD4 TFD3 HDLC.TSR HDLC Transmit Status Register 0A4h 13 12 TFFL5 TFFL4 TFFL3 157 of 230 DS3170 DS3/E3 Single-Chip Transceiver TFD2 TFD1 TFFL2 TFFL1 TFF TFE 8 TFD0 ...
Page 158
... GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled HDLC.TSRL HDLC Transmit Status Register Latched 0A6h TFOL TFUL TPEL HDLC.TSRIE HDLC Transmit Status Register Interrupt Enable 0A8h TFOIE TFUIE TPEIE 0 0 158 of 230 DS3170 DS3/E3 Single-Chip Transceiver TFEL TFEIE ...
Page 159
... HDLC Receive Status Register Latched HDLC Receive Status Register Interrupt Enable Unused HDLC Receive FIFO Data Register Unused HDLC.RCR HDLC Receive Control Register 0B0h RDAL4 RDAL3 RBRE 0 0 159 of 230 DS3170 DS3/E3 Single-Chip Transceiver RDAL2 RDAL1 RDIE RFPD RDAL0 0 0 RFRST 0 ...
Page 160
... Bit 0: Receive HDLC Data Available Latched (RHDAL) – This bit is set when the RHDA bit transitions from HDLC.RSR HDLC Receive Status Register 0B4h HDLC.RSRL HDLC Receive Status Register Latched 0B6h RPEL RPSL 160 of 230 DS3170 DS3/E3 Single-Chip Transceiver RFF RFE RFFL -- 8 -- ...
Page 161
... If bit reordering is enabled, RFD[7] is the first bit received, and RFD[0] is the last bit received. HDLC.RSRIE HDLC Receive Status Register Interrupt Enable 0B8h RPEIE RPSIE 0 0 HDLC.RFDR HDLC Receive FIFO Data Register 0BCh 13 12 RFD5 RFD4 RFD3 RPS2 0 0 161 of 230 DS3170 DS3/E3 Single-Chip Transceiver RFFIE -- RFD2 RFD1 RPS1 RPS0 ...
Page 162
... Bit 0: Receive FIFO Data Valid (RFDV) – When 0, the Receive FIFO data (RFD[7:0]) is invalid (the Receive FIFO is empty). When 1, the Receive FIFO data (RFD[7:0]) is valid. DS3170 DS3/E3 Single-Chip Transceiver 162 of 230 ...
Page 163
... FEAC Transmit Control Register FEAC Transmit Data Register FEAC Transmit Status Register FEAC Transmit Status Register Latched FEAC Transmit Status Register Interrupt Enable Unused Unused Unused FEAC.TCR FEAC Transmit Control Register 0C0h 163 of 230 DS3170 DS3/E3 Single-Chip Transceiver TFCL TFS1 TFS0 ...
Page 164
... Immediately after a reset, this bit will be set to one. FEAC.TFDR Transmit FEAC Data Register 0C2h 13 12 TFCB5 TFCB4 TFCB3 TFCA5 TFCA4 TFCA3 0 0 FEAC.TSR FEAC Transmit Status Register 0C4h FEAC.TSRL FEAC Transmit Status Register Latched 0C6h 164 of 230 DS3170 DS3/E3 Single-Chip Transceiver TFCB2 TFCB1 TFCA2 TFCA1 ...
Page 165
... When 1, the Receive FEAC controller is reset. The FEAC FIFO is emptied, any transfer in progress is halted, and all incoming data is discarded. FEAC.TSRIE FEAC Transmit Status Register Interrupt Enable 0C8h FEAC.RCR FEAC Receive Control Register 0D0h 165 of 230 DS3170 DS3/E3 Single-Chip Transceiver ...
Page 166
... GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled FEAC.RSR FEAC Receive Status Register 0D4h RFFE FEAC.RSRL FEAC Receive Status Register Latched 0D6h FEAC.RSRIE FEAC Receive Status Register Interrupt Enable 0D8h 166 of 230 DS3170 DS3/E3 Single-Chip Transceiver RFCD RFFOL RFCDL RFFOIE RFCDIE ...
Page 167
... FIFO. RFF[5] is the LSB (last bit received) of the FEAC code (C[6]), and RFF[0] is the MSB (first bit received) of the FEAC code (C[1]). The Receive FEAC FIFO data (RFF[5:0]) is updated when it is read (lower byte read). FEAC.RFDR FEAC Receive FIFO Data Register 0DCh RFF5 RFF4 RFF3 0 0 167 of 230 DS3170 DS3/E3 Single-Chip Transceiver RFF2 RFF1 ...
Page 168
... Bit 0: Transmit Bit Reordering Enable (TBRE) – When 0, bit reordering is disabled (The first bit transmitted is the MSB TT.TIR.TTD[7] of the byte). When 1, bit reordering is enabled (The first bit transmitted is the LSB TT.TIR.TTD[0] of the byte). TT.TCR Trail Trace Transmit Control Register 0E8h Reserved TMAD 0 0 168 of 230 DS3170 DS3/E3 Single-Chip Transceiver TIDLE TDIE ...
Page 169
... Trail Trace Receive Identifier Register 0FEh TT.EIR Trail Trace Expected Identifier Register TT.TTIAR Trail Trace Transmit Identifier Address Register 0EAh Reserved Reserved TTIA3 0 0 TT.TIR Trail Trace Transmit Identifier Register 0ECh TTD5 TTD4 TTD3 0 0 169 of 230 DS3170 DS3/E3 Single-Chip Transceiver TTIA2 TTIA1 TTD2 TTD1 ...
Page 170
... Fh, a memory access will return them to 0h). TT.RCR Trail Trace Receive Control Register 0F0h Reserved Reserved RMAD 0 0 TT.RTIAR Trail Trace Receive Identifier Address Register 0F2h 13 12 Reserved Reserved ETIA3 Reserved Reserved RTIA3 0 0 170 of 230 DS3170 DS3/E3 Single-Chip Transceiver RETCE RDIE ETIA2 ETIA1 RTIA2 RTIA1 ...
Page 171
... Bit 0: Receive Trail Trace Identifier Idle Latched (RIDLL) – This bit is set when the TT.RSR.RIDL bit transitions from TT.RSR Trail Trace Receive Status Register 0F4h TT.RSRL Trail Trace Receive Status Register Latched 0F6h RTICL 171 of 230 DS3170 DS3/E3 Single-Chip Transceiver RTIM RTIU RTIML RTIUL 8 -- ...
Page 172
... The receive trail trace identifier address will be incremented whenever these bits are read (when byte Fh is read, the address will return to 0h). TT.RSRIE Trail Trace Receive Status Register Interrupt Enable 0F8h RTICIE 0 0 TT.RIR Trail Trace Receive Identifier Register 0FCh RTD5 RTD4 RTD3 0 0 172 of 230 DS3170 DS3/E3 Single-Chip Transceiver RTIMIE RTIUIE RTD2 RTD1 ...
Page 173
... The expected trail trace identifier address will be incremented whenever these bits are read or written (when byte Fh is read or written, the address will return to 0h). TT.EIR Trail Trace Expected Identifier Register 0FEh ETD5 ETD4 ETD3 0 0 173 of 230 DS3170 DS3/E3 Single-Chip Transceiver ETD2 ETD1 ...
Page 174
... When 1, the RDI is inserted from the register bit TRDI. T3.TCR T3 Transmit Control Register 118h PBGE TIDLE TFEBE AFEBED TRDI and C . Note: a far-end block error value of zero (TFEBE= Note: an RDI value of zero (TRDI=1) indicates an alarm. 2 174 of 230 DS3170 DS3/E3 Single-Chip Transceiver CBGD -- ARDID TFGD TAIS 0 ...
Page 175
... For a second error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error will be inserted. T3.TEIR T3 Transmit Error Insertion Register 11Ah CCPEIE PEI FEIC1 FEIC0 0 0 175 of 230 DS3170 DS3/E3 Single-Chip Transceiver CPEI CFBEIE FEI TSEI FBEI 0 ...
Page 176
... Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled. When 1, manual downstream AIS insertion is enabled. T3.RCR T3 Receive Control Register 120h 13 12 MAOD MDAISI AAISD RAIOD RAIAD ROMD 0 0 176 of 230 DS3170 DS3/E3 Single-Chip Transceiver ECC FECC1 LIP1 LIP0 FECC0 0 ...
Page 177
... Bit 11: T3 Framing Format Mismatch (T3FM) – This bit indicates the DS3 framer is programmed for a framing format (C-bit or M23) that is different than the format indicated by the AIC bit in the incoming DS3 signal. T3.RSR1 T3 Receive Status Register #1 124h Reserved T3FM LOF 177 of 230 DS3170 DS3/E3 Single-Chip Transceiver AIC IDLE RDI AIS OOF 8 RUA1 0 ...
Page 178
... Bit 0: Framing Error Count (FEC) – When 0, the framing error count is zero. When 1, the framing error count is one or more. The type of framing error event counted is determined by T3.RCR.FECC[1:0] bit. A one indicates C-bit format and a zero indicates M23 format. 11 T3.RSR2 T3 Receive Status Register #2 126h CPEC 178 of 230 DS3170 DS3/E3 Single-Chip Transceiver FBEC PEC FEC ...
Page 179
... This bit is set to zero in M23 DS3 mode. T3.RSRL1 T3 Receive Status Register Latched #1 128h 13 12 Reserved Reserved T3FML 5 4 COFAL LOFL RAIL T3.RSRL2 T3 Receive Status Register Latched #2 12Ah CPEL CPECL 179 of 230 DS3170 DS3/E3 Single-Chip Transceiver AICL IDLEL AISL OOFL FBEL PEL FBECL PECL 8 RUA1L 0 LOSL 8 FEL 0 ...
Page 180
... Bit 4: Loss Of Frame Interrupt Enable (LOFIE) – This bit enables an interrupt if the LOFL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled T3.RSRIE1 T3 Receive Status Register Interrupt Enable #1 12Ch 13 12 Reserved Reserved T3FMIE COFAIE LOFIE RAIIE 0 0 180 of 230 DS3170 DS3/E3 Single-Chip Transceiver AICIE IDLEIE AISIE OOFIE RUA1IE 0 0 LOSIE ...
Page 181
... Bit 3: C-bit Parity Error Count Interrupt Enable (CPECIE) – This bit enables an interrupt if the CPECL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled T3.RSRIE2 T3 Receive Status Register Interrupt Enable #2 12Eh CPEIE CPECIE 0 0 181 of 230 DS3170 DS3/E3 Single-Chip Transceiver FBEIE PEIE FBECIE PECIE FEIE 0 0 FECIE ...
Page 182
... T3 Receive Framing Error Count Register 134h 13 12 FE13 FE12 FE11 FE5 FE4 0 0 T3.RPECR T3 Receive P-bit Parity Error Count Register 136h 13 12 PE13 PE12 PE11 PE5 PE4 0 0 182 of 230 DS3170 DS3/E3 Single-Chip Transceiver FE10 FE9 FE3 FE2 FE1 PE10 PE9 PE3 PE2 PE1 ...
Page 183
... T3.RCPECR T3 Receive C-bit Parity Error Count Register 13Ah 13 12 CPE13 CPE12 CPE11 CPE5 CPE4 CPE3 0 0 Register Description E3 G.751 Transmit Control Register E3 G.751 Transmit Error Insertion Register Reserved Reserved 183 of 230 DS3170 DS3/E3 Single-Chip Transceiver FBE 10 FBE9 FBE2 FBE1 CPE10 CPE9 ...
Page 184
... Bit 0: Transmit Alarm Indication Signal (TAIS) – When 0, the normal signal is transmitted. When 1, the output E3 data stream is forced to all ones (AIS). E3G751.TCR E3 G.751 Transmit Control Register 118h Reserved Reserved Reserved Reserved TABC1 0 0 184 of 230 DS3170 DS3/E3 Single-Chip Transceiver Reserved TNBC1 TABC0 TFGD TNBC0 0 ...
Page 185
... When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is one, changing the state of this bit may cause an error to be inserted. E3G751.TEIR E3 G.751 Transmit Error Insertion Register 11Ah Reserved Reserved FEIC1 FEIC0 0 0 185 of 230 DS3170 DS3/E3 Single-Chip Transceiver Reserved Reserved FEI TSEI Reserved 0 ...
Page 186
... E3 G.751 Receive Status Register Interrupt Enable #2 Reserved Reserved E3 G.751 Receive Framing Error Count Register Reserved Reserved Reserved Unused Unused E3G751.RCR E3 G.751 Receive Control Register 120h 13 12 DLS MDAISI AAISD RAIOD RAIAD ROMD 0 0 186 of 230 DS3170 DS3/E3 Single-Chip Transceiver ECC FECC1 LIP1 LIP0 FECC0 0 0 FRSYNC 0 ...
Page 187
... Bit 2: Alarm Indication Signal (AIS) – When 0, the receive frame processor is not in an alarm indication signal (AIS) condition. When 1, the receive frame processor AIS condition. E3G751.RSR1 E3 G.751 Receive Status Register #1 124h Reserved Reserved LOF 187 of 230 DS3170 DS3/E3 Single-Chip Transceiver Reserved Reserved RDI AIS OOF 8 RUA1 0 ...
Page 188
... Bit 0: Loss Of Signal Change Latched (LOSL) – This bit is set when the LOS bit changes state. E3G751.RSR2 E3 G.751 Receive Status Register #2 126h Reserved E3G751.RSRL1 E3 G.751 Receive Status Register Latched #1 128h 13 12 Reserved Reserved Reserved 5 4 COFAL LOFL RDIL 188 of 230 DS3170 DS3/E3 Single-Chip Transceiver Reserved Reserved Reserved Reserved AISL OOFL FEC 8 ...
Page 189
... E3G751.RSRL2 E3 G.751 Receive Status Register Latched #2 12Ah Reserved Reserved E3G751.RSRIE1 E3 G.751 Receive Status Register Interrupt Enable #1 12Ch 13 12 Reserved Reserved Reserved COFAIE LOFIE RDIIE 0 0 189 of 230 DS3170 DS3/E3 Single-Chip Transceiver Reserved Reserved Reserved Reserved Reserved Reserved AISIE OOFIE FEL 0 FECL ...
Page 190
... E3G751.RSRIE2 E3 G.751 Receive Status Register Interrupt Enable #2 12Eh Reserved Reserved 0 0 E3G751.RFECR E3 G.751 Receive Framing Error Count Register 134h 13 12 FE13 FE12 FE11 FE5 FE4 0 0 190 of 230 DS3170 DS3/E3 Single-Chip Transceiver Reserved Reserved Reserved Reserved FE10 FE9 FE3 FE2 FE1 ...
Page 191
... E3 G.832 Transmit Control Register E3 G.832 Transmit Error Insertion Register E3 G.832 Transmit MA Byte Register E3 G.832 Transmit NR and GC Byte Register E3G832.TCR E3 G.832 Transmit Control Register 118h Reserved Reserved TFEBE AFEBED TRDI 0 0 191 of 230 DS3170 DS3/E3 Single-Chip Transceiver TGCC TNRC1 ARDID TFGD TNRC0 0 0 TAIS ...
Page 192
... When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is one, changing the state of this bit may cause an error to be inserted. E3G832.TEIR E3 G.832 Transmit Error Insertion Register 11Ah Reserved PEI FEIC1 FEIC0 0 0 192 of 230 DS3170 DS3/E3 Single-Chip Transceiver Reserved CFBEIE FEI TSEI FBEI 0 ...
Page 193
... Bits Transmit NR Byte (TNR[7:0]) – These eight bits are the NR byte to be inserted into the E3 frame. E3G832.TMABR E3 G.832 Transmit MA Byte Register 11Ch TPT0 TTIGD TTI3 0 0 E3G832.TNGBR E3 G.832 Transmit NR and GC Byte Register 11Eh 13 12 TGC5 TGC4 TGC3 TNR5 TNR4 TNR3 0 0 193 of 230 DS3170 DS3/E3 Single-Chip Transceiver TTI2 TTI1 TGC2 TGC1 TNR2 TNR1 ...
Page 194
... E3 G.832 Receive Parity Error Count Register E3 G.832 Receive Remote Error Indication Count Register Reserved Unused Unused E3G832.RCR E3 G.832 Receive Control Register 120h 13 12 DLS MDAISI AAISD RAIOD RAIAD ROMD 0 0 194 of 230 DS3170 DS3/E3 Single-Chip Transceiver ECC FECC1 LIP1 LIP0 FECC0 0 0 FRSYNC 0 ...
Page 195
... MA byte (MA[6:8]), and stored in a register. When 1, timing source indicator bit extraction is disabled, and the last three bits of the MA byte are integrated and stored in a register. E3G832.RMACR E3 G.832 Receive MA Byte Control Register 122h EPT2 0 0 195 of 230 DS3170 DS3/E3 Single-Chip Transceiver EPT1 EPT0 ...
Page 196
... Bit 0: Framing Error Count (FEC) – When 0, the framing error count is zero. When 1, the framing error count is one or more. E3G832.RSR1 E3 G.832 Receive Status Register #1 124h RPTU RPTM LOF E3G832.RSR2 E3 G.832 Receive Status Register #2 126h Reserved 196 of 230 DS3170 DS3/E3 Single-Chip Transceiver Reserved Reserved RAI AIS OOF FBEC PEC 8 RUA1 0 LOS ...
Page 197
... E3G832.RSRL1 E3 G.832 Receive Status Register Latched #1 128h 13 12 TIL RPTUL RPTML 5 4 COFAL LOFL RDIL E3G832.RSRL2 E3 G.832 Receive Status Register Latched #2 12Ah Reserved Reserved 197 of 230 DS3170 DS3/E3 Single-Chip Transceiver RPTL Reserved AISL OOFL FBEL PEL FBECL PECL 8 RUA1L 0 LOSL 8 FEL ...
Page 198
... Bit 4: Loss Of Frame Interrupt Enable (LOFIE) – This bit enables an interrupt if the LOFL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled E3G832.RSRIE1 E3 G.832 Receive Status Register Interrupt Enable #1 12Ch 13 12 TIIE RPTUIE RPTMIE COFAIE LOFIE RAIIE 0 0 198 of 230 DS3170 DS3/E3 Single-Chip Transceiver RPTIE Reserved AISIE OOFIE RUA1IE 0 0 LOSIE ...
Page 199
... Bit 1: Parity Error Count Interrupt Enable (PECIE) – This bit enables an interrupt if the PECL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set interrupt disabled 1 = interrupt enabled E3G832.RSRIE2 E3 G.832 Receive Status Register Interrupt Enable #2 12Eh Reserved Reserved 0 0 199 of 230 DS3170 DS3/E3 Single-Chip Transceiver FBEIE PEIE FBECIE PECIE FEIE 0 0 FECIE ...
Page 200
... Bits Receive NR Byte (RNR[7:0]) – These eight bits are the integrated version of the NR byte as extracted from the E3 frame. E3G832.RMABR E3 G.832 Receive MA Byte Register 130h RPT1 RPT0 0 0 E3G832.RNGBR E3 G.832 Receive NR and GC Byte Register 132h 13 12 RGC5 RGC4 RGC3 RNR5 RNR4 RNR3 0 0 200 of 230 DS3170 DS3/E3 Single-Chip Transceiver TI3 TI2 TI1 RGC2 RGC1 RNR2 RNR1 ...