DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 57

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

10.2.2 Sources of Clock Output Pin Signals
The clock output pins can be sourced from many clock sources. The clock sources are the transmit input clocks pin
(TCLKI), the receive clock input pin (RLCLK), the recovered clock in the receive LIU, and the clock signals in the
clock rate adapter circuit (CLAD). The default clock source for the receive logic is the RLCLK pin if the LIU is
disabled; otherwise the default clock is sourced from the Rx LIU clock when the RX LIU is enabled. The default
clock source for the transmit logic is the CLAD clocks.
The LIU is enabled based on the line mode bits(LM[2:0]) (see
and CLADC are located in the port configuration registers. LIUEN is not a register bit; it is a variable based on the
line mode bits.
Table 10-1. LIU Enable Table
Table 10-2
configured. Putting the device in loopback will typically mux in a different clock than the normal clock source.
Table 10-2. All Possible Clock Sources Based on Mode and Loopback
LM[2:0]
Loop Timed
1XX
000
001
010
011
Normal
Normal
Normal
Normal
Normal
MODE
identifies the framer clock source and the line clock source depending on the mode that the device is
Table 10-1
LIUEN
0
1
1
1
0
LLB and DLB
LOOPBACK
None
PLB
DLB
LLB
Any
decodes the LM bits for LiUEN selection.
STATUS
Disabled
Disabled
Enabled
Enabled
Enabled
LIU
Rx FRAMER
Same as Tx
Same as Tx
SOURCE
RLCLK or
RLCLK or
RLCLK or
RLCLK or
CLOCK
RXLIU
RXLIU
RXLIU
RXLIU
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Tx FRAMER
Same as RX
Same as RX
SOURCE
TCLKI or
TCLKI or
TCLKI or
TCLKI or
CLOCK
CLAD
CLAD
CLAD
CLAD
Table
10-26). The bits LM[2:0], LBM[2:0], LOOPT
DS3170 DS3/E3 Single-Chip Transceiver
Same as Rx
Same as Tx
Same as Rx
Same as Rx
Same as Tx
SOURCE
RLCLK or
Tx LINE
CLOCK
RXLIUn