ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 98

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
High Voltage Configuration0 Register
Name:
Address:
Default Value:
Access:
Function:
Table 73. HVCFG0 Bit Designations
Bit
7
6
5
4
3
2
1 to 0
HVCFG0
Indirectly addressed via the HVCON high voltage interface
0x00
Read/write
This 8-bit register controls the function of high voltage circuits on the ADuC7034. This register is not an MMR and does
not appear in the Complete MMR Listing section. It is accessed indirectly via the HVCON MMR, and data is indirectly
written to or read from this register via the HVDAT MMR.
00 = LIN disabled.
01 = reserved (not LIN V2.0 compliant).
10 = LIN enabled.
11 = reserved, not used.
Description
Wake-up/STI thermal shutdown disable.
Set to 1 to disable the automatic shutdown of the wake/STI driver when a thermal event occurs.
Cleared to 0 to enable the automatic shutdown of the wake/STI driver when a thermal event occurs.
Precision oscillator enable bit.
Set to 1 to enable the precision 131 kHz oscillator. The oscillator start-up time is typically 70 μs (including a high
voltage interface latency of 10 μs).
Cleared to 0 to power down the precision 131 kHz oscillator.
Bit serial device (BSD) mode enable bit.
Set to 1 to disable the internal (LIN) pull-up and to configure the LIN/BSD pin for BSD operation.
Cleared to 0 to enable an internal (LIN) pull-up resistor on the LIN/BSD pin.
Wake-up (WU) assert bit.
Set to 1 to assert the external WU pin high.
Cleared to 0 to pull the external WU pin low via an internal 10 kΩ pull-down resistor.
Power supply monitor (PSM) enable bit.
Set to 1 to enable the power supply (voltage at the VDD pin) monitor. When IRQ3 is enabled (via IRQEN[16]), the PSM
generates an interrupt if the voltage at the VDD pin drops below 6.0 V.
Cleared to 0 to disable the power supply (voltage at the VDD pin) monitor.
Low voltage flag (LVF) enable bit.
Set to 1 to enable the LVF function. The low voltage flag can be interrogated via HVMON[3] after power-up to
determine if the REG_DVDD voltage previously dropped below 2.1 V.
Cleared to 0 to disable the LVF function.
LIN operating mode. These bits enable/disable the LIN driver.
Rev. B | Page 98 of 136