ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 95

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE
The ADuC7034 integrates several high voltage circuit functions
that are controlled and monitored through a registered interface
consisting of two MMRs, namely, HVCON and HVDAT. The
HVCON register acts as a command byte interpreter, allowing the
microcontroller to indirectly read or write 8-bit data (the value
in HVDAT) from or to one of four high voltage status or con-
figuration registers. These high voltage status and configuration
registers are not MMRs but are registers commonly referred to
as indirect registers, that is, they can only be accessed (as the
name suggests) indirectly via the HVCON and HVDAT MMRs.
The physical interface between the HVCON register and the
indirect high voltage registers is a 2-wire (data and clock) serial
interface based on a 2.56 MHz serial clock. Therefore, there is a
finite 10 μs (maximum) latency between the MCU core writing
a command into HVCON and the command or data reaching
the indirect high voltage registers. There is also a finite 10 μs
latency between the MCU core writing a command into HVCON
and the indirect register data being read back into the HVDAT
PERIPHERALS
ARM7
MCU
AND
IRQ3
(IRQEN[16])
HIGH VOLTAGE
WU DIAGNOSTIC INPUT
STI DIAGNOSTIC INPUT
LIN DIAGNOSTIC INPUT
INTERFACE
HVCON
HVDAT
MMRs
Figure 40. High Voltage Interface, Top-Level Block Diagram
HVCFG0[4]
HVCFG1[3]
HVCFG1[7]
HVCFG1[5]
SERIAL
SERIAL
CLOCK
P2.6
P2.5
DATA
Rev. B | Page 95 of 136
HIGH VOLTAGE
HIGH VOLTAGE
CONTROLLER
CONTROLLER
CONTROLLER
ATTENUATOR
DIAGNOSTIC
INTERFACE
INTERRUPT
BUFFER
SERIAL
AND
register. A busy bit (for example, Bit 0 of the HVCON when
read by MCU) can be polled by the MCU to confirm when a
read/write command is complete.
The following high voltage circuit f
monitored via this interface. Figure 40 shows the top-level
architecture of the high voltage interface and the following
related circuits:
•
•
•
•
•
•
•
•
•
HVCFG1[6]
WU DIAGNOSTIC OUTPUT
HVMON[7]
STI DIAGNOSTIC OUTPUT
HVMON[5]
LIN DIAGNOSTIC OUTPUT
P2.4
PSM—HVSTA[5]
WU—HVSTA[4]
OVER TEMP—HVSTA[3]
LIN S-SCT—HVSTA[2]
STI S-SCT—HVSTA[1]
WU S-SCT—HVSTA[0]
Precision os
Wake-up (WU) pin f
Power supply monitor (PSM)
Low voltage flag (LVF)
LIN operating modes
STI diagnostics
High voltage dia
High voltage attenuator-b
High voltage (HV) temperature monitor
HIGH VOLTAGE
REGISTERS
(INDIRECT)
HVCFG0
HVCFG1
HVMON
HVSTA
MONITOR
HV TEMP
cillator
HVCFG0[6]
HVCFG0[3]
HVCFG0[2]
gnostics
HVCFG0[1:0]
HVCFG0[5]
HVCFG0[4]
HVCFG1[4]
HVCFG1[4]
HVCFG1[3]
unctionality
uffer circuit
unctions are controlled and
OSCILLATOR
PRECISION
CONTROL
CONTROL
MODES
WU I/O
STI I/O
PSM
LVF
LIN
ADuC7034