ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 27

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Command Sequence for Executing a Mass Erase
Given the significance of the mass erase command, a specific
code sequence must be executed to initiate this operation:
1.
2.
3.
4.
This sequence is illustrated in the following example:
FEE0MOD = 0x08;
FEE0ADR = 0xFFC3;
FEE0DAT = 0x3CFF;
FEE0CON = 0x06;
command
while (FEE0STA & 0x04){} //Wait for
command to finish
FEE0STA Register
Name:
Address:
Default Value:
Access:
Function:
Table 14. FEE0STA MMR Bit Designation
Bit
7 to 4
3
2
1
0
Set Bit 3 in FEE0MOD.
Write 0xFFC3 in FEE0ADR.
Write 0x3CFF in FEE0DAT.
Run the mass erase command (Code 0x06) in FEE0CON.
Description
Not used. These bits are not used and always read as 0.
Flash/EE interrupt status bit.
Set automatically when an interrupt occurs, that is,
when a command is complete and the Flash/EE
interrupt enable bit in the FEE0MOD register is set.
Cleared automatically when the FEE0STA register is
read by user code.
Flash/EE controller busy.
Set automatically when the Flash/EE controller is busy.
Cleared automatically when the controller is not busy.
Command fail.
Set automatically when a command written to
FEE0CON fails.
Cleared automatically when the FEE0STA register is
read by user code.
Command successful.
Set automatically by MCU when a command is
completed successfully.
Cleared automatically when the FEE0STA register is
read by user code.
FEE0STA
0xFFFF0E00
0x20
Read only
This 8-bit, read only register can be read by
user code and reflects the current status of the
Flash/EE memory controller.
//Mass erase
Rev. B | Page 27 of 136
FEE0MOD Register
Name:
Address:
Default Value:
Access:
Function:
Table 15. FEE0MOD MMR Bit Designation
Bit
7
6 to 5
4
3
2
1
0
FEE0ADR Registers
Name:
Address:
Default Value:
Access:
Function:
Description
Not used. These bits are reserved for future functionality
and should be written as 0 by user code.
Flash/EE security lock bits. These bits must be written as
[6:5] = 10 to complete the Flash/EE security protect
sequence.
Flash/EE controller command complete interrupt enable.
Set to 1 by user code to enable the Flash/EE controller
to generate an interrupt upon completion of a Flash/EE
command.
Cleared to disable the generation of a Flash/EE
interrupt upon completion of a Flash/EE command.
Flash/EE erase/write enable.
Set by user code to enable the Flash/EE erase and write
access via FEE0CON.
Cleared by user code to disable the Flash/EE erase and
write access via FEE0CON.
Reserved.
Flash/EE controller abort enable.
Set to 1 by user code to enable the Flash/EE controller
abort functionality.
Cleared by user code to disable the Flash/EE controller
abort functionality.
Reserved.
FEE0ADR
0xFFFF0E10
Nonzero, see the
System Identification Register section
Read/write access
This 16-bit register dictates the address acted
upon when a Flash/EE command is executed
via FEE0CON.
FEE0MOD
0xFFFF0E04
0x00
Read/write access
This register is written by user code to
configure the mode of operation of the
Flash/EE memory controller.
ADuC7034