ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 51

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC Configuration Register
Name:
Address:
Default Value:
Access:
Function:
Table 41. ADCCFG MMR Bit Designations
Bit
7
6 to 5
4 to 3
2
1
0
ADCCFG
0xFFFF051C
0x00
Read/write
The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs.
Description
Analog ground switch enable.
Set to 1 by user software to connect the external GND_SW pin (Pin 15) to an internal analog ground reference point.
This bit can be used to connect and disconnect external circuits and components to ground under program control and
thereby minimize dc current consumption when the external circuit or component is not being used. This bit is used in
conjunction with ADCMDE[6] to select a 20 kΩ resistor to ground.
Cleared by user code to disconnect the external GND_SW pin.
Current channel (32-bit) accumulator enable.
00 = accumulator disabled and reset to 0. The accumulator must be disabled for a full ADC conversion (ADCSTA[0] set
twice) before the accumulator can be re-enabled to ensure the accumulator is reset.
01 = accumulator active.
Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535
conversions.
Negative current values are subtracted from the accumulator total; the accumulator is clamped to a minimum value of 0.
10 = accumulator active.
Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535
conversions.
The absolute values of negative current are subtracted from the accumulator total; the accumulator in this mode
continues to subtract current even after 0 is reached.
11 = not defined.
Current channel ADC comparator enable.
00 = comparator disabled.
01 = comparator active. An interrupt is asserted if the absolute value of the I-ADC conversion result is |I| ≥ ADC0TH.
10 = comparator count reset mode active. An interrupt is asserted if the absolute value of the I-ADC conversion result is
|I| ≥ ADC0TH for the number of ADC0TCL conversions. A conversion value of |I| < ADC0TH resets the threshold counter
value (ADC0THV) to 0.
11 = comparator count decrement mode active. An interrupt is asserted if the absolute value of the I-ADC conversion
result is |I| ≥ ADC0TH for the number of ADC0TCL conversions. A conversion value of |I| < ADC0TH decrements the
threshold counter value (ADC0THV) toward 0.
Current channel ADC overrange enable.
Set by user code to enable a coarse comparator on the current channel ADC. If the current reading is more than approximately
30% overrange for the active gain setting, the overrange bit in the ADCSTA MMR is set. The current must be outside the
set range for more than 125 μs for the flag to be set. This feature should not be used in ADC low power mode.
Cleared by user code to disable the overrange feature.
Not used. This bit is reserved for future functionality and should be written as 0 by user code.
Current channel ADC, result counter enable.
Set by user to enable the result count mode. In this mode, an I-ADC interrupt is generated only when ADC0RCV = ADC0RCL.
This allows the I-ADC to continuously monitor current and interrupt the MCU core only after a defined number of
conversions. The voltage/temperature ADC also continues to convert if enabled, but only the last conversion result is
available (intermediate V-/T-ADC conversion results are not stored) when the ADC counter interrupt occurs.
Rev. B | Page 51 of 136
ADuC7034