ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 68

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 16 interrupt sources on the ADuC7034 that are
controlled by the interrupt controller. Most interrupts are
generated from the on-chip peripherals, such as the ADC and
UART. The ARM7TDMI CPU core only recognizes interrupts
as one of two types: a normal interrupt request (IRQ) and a fast
interrupt request (FIQ). All the interrupts can be masked
separately.
The control and configuration of the interrupt system is
managed through nine interrupt-related registers, with four
dedicated to IRQ, four dedicated to FIQ, and one used to select
the programmed interrupt source. As is described in Table 49,
the selected interrupt source applies to the corresponding bits of
the IRQ and FIQ registers.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
Table 49. IRQ/FIQ MMRs Bit Designations
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Description
All interrupts OR’ed (FIQ only)
SWI: not used in IRQEN/CLR and FIQEN/CLR
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4 or STI timer
LIN hardware
Flash/EE interrupt
PLL lock
ADC
UART
SPI master
XIRQ0 (GPIO IRQ0 )
XIRQ1 (GPIO IRQ1)
Reserved
IRQ3 high voltage IRQ
SPI slave
XIRQ4 (GPIO IRQ4)
XIRQ5 (GPIO IRQ5)
Rev. B | Page 68 of 136
Comments
See the Timer0—Lifetime Timer section.
See the Timer1 section.
See the Timer2—Wake-Up Timer section.
See the Timer3—Watchdog Timer section.
See the Timer4—STI Timer section.
See the LIN (Local Interconnect Network) Interface section.
See the Flash/EE Control Interface section.
See the ADuC7034 System Clocks section.
See the 16-Bit Sigma-Delta Analog-to-Digital Converters section.
See the UART Serial Interface section.
See the Serial Peripheral Interface section.
See the General-Purpose I/O section.
See the General-Purpose I/O section.
High voltage interrupt; see the High Voltage Peripheral Control
Interface section.
See the Serial Peripheral Interface section.
See the General-Purpose I/O section.
See the General-Purpose I/O section.
The interrupt generation route through the ARM7TDMI core is
shown in Figure 31.
Consider an example where Timer0 is configured to generate
a timeout every 1 ms. After the first 1 ms timeout, FIQSIG/
IRQSIG[2] is set and can only be cleared by writing to T0CLRI.
If Timer0 is not enabled in either IRQEN or FIQEN, then FIQSTA/
IRQSTA[2] is not set and an interrupt does not occur. However,
if Timer0 is enabled in either IRQEN or FIQEN, then either
FIQSTA/IRQSTA[2] is set or an interrupt (FIQ or IRQ) occurs.
Note that the IRQ and FIQ bit definitions in the CPSR ARM
register only control interrupt recognition by the ARM core, not
by the peripherals. For example, if Timer2 is configured to generate
an IRQ via IRQEN, the IRQ interrupt bit is set (disabled) in the
CPSR and the ADuC7034 is powered down. When an interrupt
occurs, the peripherals wake up, but the ARM core remains
powered down. This is equivalent to POWCON = 0x71. The
ARM core can then only be powered up by a reset event.