ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 71

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMERS
The ADuC7034 features five general-purpose timer/counters.
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The five timers in their normal mode of operation can be in
either free running mode or periodic mode.
Timers are started by writing data to the control register of the
corresponding timer (TxCON). The counting mode and speed
depend on the configuration chosen in TxCON.
In normal mode, an IRQ is generated each time the value of
the counter reaches 0 when counting down, or each time the
counter value reaches full scale when counting up. An IRQ
can be cleared by writing any value to clear the register of
that particular timer (TxCLRI).
The three timers in their normal mode of operation can be
either free-running or periodic.
In free-running mode, starting with the value in the TxLD
register, the counter decrements/increments from the maximum/
minimum value until zero/full scale and starts again at the
maximum/minimum value. This means that, in free-running
mode, TxVAL is not reloaded when the relevant interrupt bit is
set but the count simply rolls over as the counter underflows or
overflows.
In periodic mode, the counter decrements/increments from
the value in the load register (TxLD MMR) until zero/full scale
starts again from this value. This means when the relevant
interrupt bit is set, TxVAL is reloaded with TxLD and counting
starts again from this value.
Loading the TxLD register with zero is not recommended. The
value of a counter can be read at any time by accessing its value
register (TxVAL).
In addition, Timer0, Timer1, and Timer4 each have a capture
register (T0CAP, T1CAP, and T4CAP, respectively) that can
Timer0, or the lifetime timer
Timer1, or general-purpose timer
Timer2, or the wake-up timer
Timer3, or the watchdog timer
Timer4, or the STI timer
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hold the value captured by an enabled IRQ event. The IRQ
events are described in Table 51.
Table 51. Timer Event Capture
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SYNCHRONIZATION OF TIMERS ACROSS
ASYNCHRONOUS CLOCK DOMAINS
The block diagram in Figure 32 shows the interface between
user timer MMRs and the core timer blocks. User code can
access all timer MMRs directly, including TxLD, TxVAL,
TxCON, and TxCLRI. Data must then transfer from these
MMRs to the core timers (T0, T1, T2, T3, and T4) within the
timer subsystem. Theses core timers are buffered from the
user MMR interface by the synchronization (SYNC) block.
The principal of the SYNC block is to provide a method that
ensures that data and other required control signals can cross
asynchronous clock domains correctly. An example of asyn-
chronous clock domains is the MCU running on the 10 MHz
core clock, and Timer2 running on the low power oscillator of
32 kHz.
Description
Timer0, or the lifetime timer
Timer1, or general-purpose timer
Timer2, or the wake-up timer
Timer3, or the watchdog timer
Timer4, or the STI timer
LIN hardware
Flash/EE interrupt
PLL lock
ADC
UART
SPI master
XIRQ0 (GPIO_0)
XIRQ1 (GPIO_5)
Reserved
IRQ3 high voltage interrupt
SPI slave
XIRQ4 (GPIO_7); see the General-Purpose I/O section
XIRQ5 (GPIO_8); see the General-Purpose I/O section
ADuC7034