ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 127

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BSD RELATED MMRS
The ADuC7034 emulates the BSD communication protocol
using a software (bit bang) interface with some hardware assis-
tance from the LIN hardware synchronization logic. In effect,
the ADuC7034 BSD interface uses the following protocols:
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The ADuC7034 MMRs required for BSD communication are as
follows:
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Detailed bit definitions for most of these MMRs have been
listed previously. In addition to the registers described in the
LIN MMR Description section, LHSCAP and LHSCMP are
new registers that are required for the operation of the BSD
An internal GPIO signal (GPIO_12) that is routed to the
external LIN/BSD pin and is controlled directly by
software to generate 0s and 1s.
When reading bits, the LIN synchronization hardware uses
LHSVAL1 to count the width of the incoming pulses so
that user code can interpret the bits as sync, 0, or 1.
When writing bits, user code toggles a GPIO pin and uses
the LHSCAP and LHSCMP registers to time pulse widths
and generate an interrupt when the BSD output pulse
width has reached its required width.
LHSSTA: LIN hardware sync status register.
LHSCON0: LIN hardware sync control register.
LHSVAL0: LIN Hardware Sync Timer0 (16-bit timer).
LHSCON1: LIN hardware sync edge setup register.
LHSVAL1: LIN sync break timer.
LHSCAP: LIN sync capture register.
LHSCMP: LIN sync compare register.
IRQEN/CLR: Enable interrupt register.
FIQEN/CLR: Enable fast interrupt register.
GP2DAT: GPIO data register.
GP2SET: GPIO set register.
GP2CLR: GPIO clear register.
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interface. Details of these registers are included in the LIN
Hardware Synchronization Capture Register and LIN Hardware
Synchronization Compare Register sections.
LIN Hardware Synchronization Capture Register
Name:
Address:
Default Value:
Access:
Function:
LIN Hardware Synchronization Compare Register
Name:
Address:
Default Value:
Access:
Function:
LHSCAP
0x0000
Read only
This 16-bit, read only LHSCAP register holds
the last captured value of the internal LIN
synchronization timer (LHSVAL0). In BSD
mode, the LHSVAL0 is clocked directly from
an internal 5 MHz clock, and its value is
loaded into the capture register on every
falling edge of the BSD bus.
LHSCMP
0x0000
Read/write
The LHSCMP register is used to time BSD
output pulse widths. When enabled through
LHSCON0[5], a LIN interrupt is generated
when the value in LHSCAP equals the value
written in LHSCMP. This functionality allows
user code to determine how long a BSD
transmission bit (sync, 0, or 1) should be
asserted on the bus.
0xFFFF0794
0xFFFF0798
ADuC7034