ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 24

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
RESET
There are four kinds of resets: external reset, power-on reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can be written to by
user code to initiate a software reset event. The bits in this
register can be cleared to 0 by writing to the RSTCLR MMR.
The bit designations in RSTCLR mirror those of RSTSTA.
These registers can be used during a reset exception service
routine to identify the source of the reset. The implications of
all four kinds of reset events are tabulated in Table 12.
RSTSTA Register
Name:
Address:
Default Value:
Access:
Function:
Table 12. Device Reset Implications
Reset
POR
Watchdog
Software
External Pin
1
2
RAM is not valid in the case of a reset following a LIN download.
The impact on RAM is dependent on the HVMON[3] contents if LVF is enabled. When LVF is enabled using HVCFG0[2], RAM has not been corrupted by the POR reset
mechanism if the LVF status bit, HVMON[3], is 1. See the Low Voltage Flag (LVF) section for more information.
Reset
External Pins
to Default
State
Yes
Yes
Yes
Yes
RSTSTA
0xFFFF0230
Depends on type of reset
Read/write access
This 8-bit register indicates the source of the
last reset event and can be written to by user
code to initiate a software reset.
Execute
Kernel
Yes
Yes
Yes
Yes
Reset All
External MMRs
(Excluding
RSTSTA)
Yes
Yes
Yes
Yes
Rev. B | Page 24 of 136
Reset All HV
Indirect
Registers
Yes
Yes
Yes
Yes
Impact
RSTCLR Register
Name:
Address:
Access:
Function:
Table 11. RSTSTA/RSTCLR MMR Bit Designations
Bit
7 to 4
3
2
1
0
1
clear this bit generates a software reset.
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
Reset
Peripherals
Yes
Yes
Yes
Yes
RSTCLR
0xFFFF0234
Write only
This 8-bit write only register clears the
corresponding bit in RSTSTA.
Description
Not used. These bits are not used and always
read as 0.
External reset.
Software reset.
Set to 1 by user code to generate a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Watchdog timeout.
Set automatically to 1 when a watchdog timeout
occurs.
Cleared by setting the corresponding bit in RSTCLR.
Power-on reset.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
Set automatically to 1 when an external reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
Reset
Watchdog
Timer
Yes
No
No
No
Valid
RAM
Yes/No
Yes
Yes
Yes
1
2
RSTSTA Status
(After a Reset
Event)
RSTSTA[0] = 1
RSTSTA[1] = 1
RSTSTA[2] = 1
RSTSTA[3] = 1
1