ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 74

IC,Battery Management,LLCC,48PIN,PLASTIC

ADUC7034BCPZ-RL

Manufacturer Part Number
ADUC7034BCPZ-RL
Description
IC,Battery Management,LLCC,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet

Specifications of ADUC7034BCPZ-RL

Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADuC7034
TIMER0—LIFETIME TIMER
Timer0 is a general-purpose, 48-bit up counter or a 16-bit
up/down counter timer with a programmable prescaler. Timer0
can be clocked from either the core clock or the low power
32.768 kHz oscillator with a prescaler of 1, 16, 256, or 32,768.
When the core is operating at 20.48 MHz with a prescaler of 1,
a minimum resolution of 48.83 ns results.
In 48-bit mode, Timer0 counts up from 0. The current counter
value can be read from T0VAL0 and T0VAL1.
In 16-bit mode, Timer0 can count up or down. A 16-bit value
can be written to T0LD to load into the counter. The current
counter value is read from T0VAL0. Timer0 has a capture
register (T0CAP) that is triggered by a selected IRQ source
initial assertion. When the capture register is triggered, the
current timer value is copied to T0CAP and the timer continues
running. This feature can be used to determine the assertion of
an event with more accuracy than would be provided by
servicing an interrupt alone.
Timer0 reloads the value from T0LD when Timer0 overflows.
The Timer0 interface consists of six MMRS.
T0LD is a 16-bit register holding the 16-bit value that is loaded
into the counter. T0LD is only available in 16-bit mode.
T0CAP is a 16-bit register that holds the 16-bit value
captured by an enabled IRQ event. T0CAP is only available
in 16-bit mode.
T0VAL0/T0VAL1 are 16-bit and 32-bit registers that hold
the 16 LSBs and 32 MSBs, respectively. T0VAL0 and
T0VAL1 are read only registers. In 16-bit mode, 16-bit
T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0 and
32-bit T0VAL1 are used.
T0CLRI is an 8-bit register. Writing any value to this
register clears the interrupt. T0CLRI is only available in
16-bit mode.
T0CON is a configuration MMR and is described in Table 52.
Rev. B | Page 74 of 136
Timer0 Load Register
Name:
Address:
Default Value:
Access:
Function:
Timer0 Clear Register
Name:
Address:
Access:
Function:
Timer0 Value Registers
Name:
Address:
Default Value:
Access:
Function:
Timer0 Capture Register
Name:
Address:
Default Value:
Access:
Function:
T0CLRI
0xFFFF0310
Write only
This 8-bit, write only MMR is written (with
any value) by user code to clear the interrupt.
T0LD
0xFFFF0300
0x0000
Read/write
T0LD0 is the 16-bit register holding the 16-bit
value that is loaded into the counter. This
register is only available in 16-bit mode.
T0VAL0, T0VAL1
0xFFFF0304, 0xFFFF0308
0x0000, 0x00000000
Read access only
T0VAL0 and T0VAL1 are 16-bit and 32-bit
registers that hold the 16 LSBs and 32 MSBs,
respectively. T0VAL0 and T0VAL1 are read only
registers. In 16-bit mode, 16-bit T0VAL0 is
used. In 48-bit mode, both 16-bit T0VAL0 and
32-bit T0VAL1 are used.
T0CAP
0xFFFF0314
0x0000
Read access only
This is a 16-bit register that holds the 16-bit
value captured by an enabled IRQ event. This
register is only available in 16-bit mode.

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