ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 54

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
Current Channel ADC Result Counter Limit Register
Name:
Address:
Default Value:
Access:
Function:
Current Channel ADC Result Count Register
Name:
Address:
Default Value:
Access:
Function:
Current Channel ADC Threshold Register
Name:
Address:
Default Value:
Access:
Function:
ADC0RCL
0xFFFF0548
0x0001
Read/write
This 16-bit MMR sets the number of
conversions required before an ADC interrupt
can be generated. By default, this register is set to
0x01. The ADC counter function must be
enabled via the ADC result counter enable bit
in the ADCCFG MMR.
ADC0RCV
0xFFFF054C
0x0000
Read only
This 16-bit, read only MMR holds the current
number of I-ADC conversion results. It can be
used in conjunction with the ADC0RCL
register to mask I-ADC interrupts and
therefore generate a lower interrupt rate.
Alternatively, the ADC0RCV register can be used
in conjunction with the accumulator
(ADC0ACC) to calculate the average current. In
either case, the result counter must be enabled
via ADCCFG[0]. When ADC0RCV =
ADC0RCL, the value in ADC0RCV resets to 0
and resumes counting. In addition, the value
in ADC0RCV resets to 0 when the I-ADC is
reconfigured, that is, when the ADC0CON or
ADCMDE are written.
ADC0TH
0xFFFF0550
0x0000
Read/write
This 16-bit MMR sets the threshold that is
compared with the absolute value of the I-ADC
conversion result. In unipolar mode, this
threshold is compared with ADC0TH[15:0]; in
twos complement mode, this threshold is
compared with ADC0TH[14:0].
Rev. B | Page 54 of 136
Current Channel ADC Threshold Count Limit Register
Name:
Address:
Default Value:
Access:
Function:
Current Channel ADC Threshold Count Register
Name:
Address:
Default Value:
Access:
Function:
Current Channel ADC Accumulator Register
Name:
Address:
Default Value:
Access:
Function:
ADC0TCL
0xFFFF0554
0x01
Read/write
This 8-bit MMR determines how many
cumulative I-ADC conversion result readings
above ADC0TH (that is, values that are below
the threshold decrement or that reset the count
to 0) must occur before the I-ADC comparator
threshold bit is set in the ADCSTA MMR,
generating an ADC interrupt. The I-ADC
comparator threshold bit is asserted as soon as
ADC0THV = ADC0TCL.
ADC0THV
0xFFFF0558
0x00
Read only
This 8-bit MMR is incremented every time the
absolute value of an I-ADC conversion result is
|I| ≥ ADC0TH. This register is decremented or
reset to 0 every time the absolute value of an I-
ADC conversion result is |I| < ADC0TH. The
configuration of this function is enabled via the
current channel ADC comparator bits in the
ADCCFG MMR.
ADC0ACC
0xFFFF055C
0x00000000
Read only
This 32-bit MMR holds the current
accumulator value. The I-ADC ready bit in the
ADCSTA MMR should be used to determine
when to read this MMR. The MMR value is
reset to 0 by disabling the accumulator in the
ADCCFG MMR or by reconfiguring the
current channel ADC.